Problem in detection of Start and stop in I2C protocol

[Mkanimozhi]

i2c protocol start stop

Hi,
I need I2C start and stop condition check code either in vhdl or in veilog, i using i am designing I2C eeprom to implement the I2c protocol, I don't know how to write the code to detect teh start and stop condition in the level of the scl ,thanks in advance

kanimozhi

 

[Mkanimozhi]

Hi,
I can't understand from that site, I need some sample code could u provide an y one for I2C start and stop bit detection in scl level triggering

kani

 

[sujithchakra]

Have look at the below site. It has free IPs of I2C EEPROMs.

http://www.young-engineering.com/intellectual_property.html

Hope this helps!

 

[FvM]

Have look at the below site. It has free IPs of I2C EEPROMs.

If you look sharp, you'll notice that it's intended as simulation model. Particularly, it's using unsynthesizable dual-edge flip-flops.

Basically, an I2C slave can be either realized fully synchronously, if a system clock is available in the design, or asynchrounously. An asynchronous design has to use some tricks to provide the SDA dual-edge start/stop detection. I didn't yet try, but it shouldn't be too complicated, I think.