syedahmar
Member level 1
hello everybody!!!
i am facing a small problem which i hope someone would solve..
i am designing a memory module which have 4 FIFOs. There in verilog code , i have an inout port DATA[31:0] and a 32 bit register data_bus.
Now during simulation, i want that when my signal rd_en is high, the contents of data_bus should be written to the inout port DATA. I have checked in simulation ,the data is there in data_bus but it doesnt write it to DATA.
my code is something like this....
assign DATA=(rd_en)?data_bus:32'bz;
During simulation, even when the rd_en signal is active, the data in DATA is the one which i had entered while rd_en was low....
Help plzzzz
i am facing a small problem which i hope someone would solve..
i am designing a memory module which have 4 FIFOs. There in verilog code , i have an inout port DATA[31:0] and a 32 bit register data_bus.
Now during simulation, i want that when my signal rd_en is high, the contents of data_bus should be written to the inout port DATA. I have checked in simulation ,the data is there in data_bus but it doesnt write it to DATA.
my code is something like this....
assign DATA=(rd_en)?data_bus:32'bz;
During simulation, even when the rd_en signal is active, the data in DATA is the one which i had entered while rd_en was low....
Help plzzzz