Pre-Layout Verification

[semi]

I need some help regarding the topic. I'm new in this field.
I have done a RTL verfication and it pass.
Now I want to do pre-layout verification, do I need to use the same testbench or have to toggle the input ealier?
What I mean is, for RTL, the testbench toggle the input to my block at posedge clk. For pre-layout, do I need to toggle the input ealier? Maybe 4-6ns from positive edge clk. I'm using 12ns for one clock cycle.

Thanks

 

[RP]

Hi,

how did you define pre-layout verification ?

As far as i am concerned, we use simulation-based and/or formal verification
to verify RTL code, and use equivalent checking tool to check layout against RTL,
and use STA for timing-verification.

RP,

 

[semi]

Hi RP,

What I mean by pre-layout is netlist after synthesis. I have done RTL verification. Then my boss asked me to synthesis the RTL and verify it using ModelSim. RTL has no delay but after synthesis, my design have delay because it has been target to a library. So, how should I verify this netlist? Using same testbench?

Thanks

 

[ami]

Hi,
You can verify the pre-layout netlist following these steps:

1.using your RTL level testbench (note that you may not use the signal-dump as in RTL level, because the signal name has been changed)

2. using the gate simulation library (ask your vendor), each AND,OR,XOR... have a fixed delay.

3(optional). you may read in the pre-layout SDF file (estimated wireload) for simulation

Hope this help,
Rgrds

 

[semi]

Hi ami,

I already done these 3 step. But for step 1, I have some argument with my friend(also new in ASIC). He said that I need to trigger the input earlier. That why we seek for guidance from experience people.

Thanks for your help

 

[Elias.xie]

Yes, if you do sdf-annotated simulation, the stimulus should also abey the timing.

 

[ami]

Hi semi,
In gate level simulation, I/O timing should(must) satisfy the characteristic/requirement (delay/edge relationship with clock,...).
Rgrds,