Power Noise in Analog Chips

[neoflash]

I'm designing high speed clocking chips. As we know, every kind of PLL has certain kind of vulnerability, more or less, to supply noise.

If customer clearly defines the possible noise amplitude and frequency on the chips, we could derive whether our chips could tolerate it.

However, it seems that there is no such kind of specifications. What is the rule of thumb?

 

[tlihu]

If you're designing Op-amp, PSRR is a useful measure.

 

[zhangsai04]

Someone use LDO before PLL,then the PLL's supply is clear.

 

[neoflash]

Don't customer put some spec on it?

 

[zhangsai04]

PLL's spec of phase noise may conclude those noises.

 

[chenmy]

Hi,neoflash:

From the design perspective,

First,you can run ac simulation and see the PSR from VDD to VCTRL of VCO (the chargepump should be turned off,and the loop filter and VCO should be added) you should make the PSR less than -90dB @ frequency larger than the PLL bandwidth.

Also,you can run simulation with VDD+-10% to see the DC supply sensitity of the VCO.

Best wishes!

chenmy