post synthesis simulution using modelsim

[smqasim]

can anybody give me the steps to perform post-synthesis simulation /back-annotation using modelsim and xilinx alliance in detail.

 

[Kulprashant]

hi,
post layout simulation needs .sdf file, test bench and rtl as inputs.
load design window of the modelsim editor you will find the .sdf file upload option.
i hope you got my point
try for this
with regards,
kul.

 

[Renjith]

have u written a testbench for ur prgm?
if so, ise will give clear links for doing post-synthesis, post-P&R simulations. so easily u can do this thrg the gui.

 

[darylz]

you cannot use rtl design code for post-synthesis simulation. the synthesis tools will give out a vhdl and a sdf file or a verilog file for you to do it.

 

[gold_kiss]

Hi,
Once you are done with synthesis. You will have your Netlist and your SDF file.
In case u use FPGA synthesis then you need Simprims

Now you need to add the SDF file in ur test bench. You can do this by $sdf_annotate("*.sdf");

or optionally you can tell the simulator to pick the SDF file during run time or compile time.

You also need to add delays in ur testbech.
u can use a better off `ifdef or `ifndef so ..for ur normal simulations and for netlist simulation you can choose on as compile time options

you need more detailed ...? PM me.

Gold_kiss