Post layout simulation problem

[PARAMSETTY DIWAKAR]

Dear all,

i did prelayout and postlayout simulation of an opamp,in prelayout simulation all transistors are working in saturation and gain is good 64 dB,but where as in post layout simulation,few transistors going to linear and gain falls to 50 dB,how can i get the transistors in saturation in post layout simulation with out changing the layout .

Please help me

Thanks in advance.

Diwakar P

p.diwa453@gmail.com

 

[erikl]

how can i get the transistors in saturation in post layout simulation with out changing the layout .

In simulation: simply decrease Vth
In process: simply decrease Vth implant dose
SCNR! ;-)
It's the government. It doesn't have to make sense. (B. Kaplow)

 

[eecs4ever]

to be in saturation, Vds > Vgs-Vt

if you decrease Vt, it will be more likely to fall out of saturation

Try to decrease the amount of total current in your op-amp, starting with the tail current source. Figure out which transistors are falling out of saturation and why.