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Post Layout Simulation (Back-annotation) - Cadence Spectre

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acey80

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cadence parasitic back annotation

Hi all,

I want to check the layout performance compared to the circuit.
I remember we have to extract the layout for parasitic values..
And so, I have:
1-circuit schematic
2-extracted (parasitic)

then, what are other settings i have to do?

thanks in advance....

cheers!
 

post-layout simulations on spectre

acey80 said:
Hi all,

I want to check the layout performance compared to the circuit.
I remember we have to extract the layout for parasitic values..
And so, I have:
1-circuit schematic
2-extracted (parasitic)

then, what are other settings i have to do?

thanks in advance....

cheers!

You can use either config or simply insert your extracted view before your schematic view in your "analog enviroment" settings, and then run your simulation as before.

Cheers!
 

backannote parasitics cadence

Hi acey80,

After extraction of RC you will get extracted view <filename>_extracted.

just go for schematic window find parasitics or parameters in 1st tab.
after that you will get a new tab called parasitics.in parasitics tab you will get back annotation option. next one import parasitics window will appear. just import extracted values from <filename>_extracted.

then do simulation as usual as simple schematic.
 

cadence spect

In the pre-simulation schematic veiw, build a config file, replace the schematic file with your extracted file in the popup config dialogue box, Run the just simulation file, the results you get this time are post-simulation ones
 

Re: Post Layout Simulation (Back-annotation) - Cadence Spect

Hi acey80,

Could you tell me how to extract parasitic values in Diva (Cadence)

Thanks and Best Regards,
 

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