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Plz help me to link these modules in verilog

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nitheeshnas

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i am doing a project on designing an ic for controlling the speed of a dc motor . the main modules in my project are pwm ,encoder,counter and pid..
i have generated the codes for counter, pid and pwm seperately but when i try to link it ..i am not getting it right ...plz help me..

these are my there modules

1,counter


Code Verilog - [expand]
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module count(clk,a,out,r,n,e);
input clk;
input a;
input [7:0]r;
input [7:0]n;
integer counter=0; 
output reg [7:0]e;
output reg [7:0]out;
reg [7:0]temp;
always @ (a)
begin
    if (a==1) counter=counter+1;
    temp=(counter/r);
    out=(temp*n);
    if
    (out>=200) e=out-200;
    else
    e=200-out;
    end
    endmodule



2,pid


Code Verilog - [expand]
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module PIDdddd(u_out,e_in,clk,reset,u);
output signed [15:0] u_out;
output signed [15:0] u;
input signed [15:0] e_in;
input clk;
input reset;
parameter k1=107;
parameter k2 = 104;
parameter k3 = 2;
reg signed [15:0] u_prev;
reg signed [15:0] e_prev1;
reg signed [15:0] e_prev2;
assign err=(e_in/5);
assign u =(u_prev)+(k1*err)+(k3*e_prev2);
assign u_out = u+(-(k2*e_prev1));
always @ (posedge clk)
if (reset == 1) begin
u_prev <= 0;
e_prev1 <= 0;
e_prev2 <= 0;
end
else begin
e_prev2 <= e_prev1;
e_prev1 <= err;
u_prev <= u_out;
end
endmodule



3,pwm


Code Verilog - [expand]
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module pulse(clk,switches,pwm);
    input clk;
    input [16:0] switches;
    output pwm;
    reg pwm;
    reg [15:0] counter=0;
    parameter sd=195;
    always @ (posedge clk)
    begin
        counter=counter+5;
        if(counter<=switches*sd) pwm=1;
        else pwm=0;
       if (counter>=50000) counter=0;
     end
 endmodule




and i want to connect these 3 modules that is i want to input the output of counter to pid and output of pid to pwm...plz help me
 
Last edited by a moderator:

If it just how to connect between 3 modules, then..
you can create another module as a top module and connect all your modules(counter, pid etc...) inside this top module as what you said
i want to input the output of counter to pid and output of pid to pwm
 

how will i do it..can u help me plz....or show me an example...
 

you can create a top module where you can instantiate all the other modules. like as follows ..

module TopModule(outputs & inputs here of the whole box containing the small boxes);
output ...
input .....

wire *instantiate some wires here to connect the modules among themselves*

//Now instantiate the modules in the following code. Read up on module instantiation. Just google it. Its pretty simple.

count counteri1(.............)
pid pidi1(...........)
pulse pulsei1(.............)
endmodule
 

Plz help me to link these modules in verilog

You must draw a simple draft diagram showing what exactly do you want to connect.



+++
 

Technically speaking you *should* TEST your individual modules first! And, by including them into a testbench file individually to make sure they work as expected in simulation, you will also learn how to connect them up in an upper level file to each other!
 

here i am adding the code for 3 modules counter,pid and pwm...plzz help me to link these three modules....in such a way that i want the output of counter to be given as the error signal input of pid(e_in) and the out put of pid (u_out) as the the input of pwm(switches)....plzz help....thanks in advance..

Code:
module count(clk,a,out,r,n,e);
input clk;
input a;
input [7:0]r;
input [7:0]n;
integer counter=0; 
output reg [7:0]e;
output reg [7:0]out;
reg [7:0]temp;
always @ (a)
begin
    if (a==1) counter=counter+1;
    temp=(counter/r);
    out=(temp*n);
    if
    (out>=200) e=out-200;
    else
    e=200-out;
    end
    endmodule





Code:
module PIDdddd(u_out,e_in,clk,reset,u);
output signed [15:0] u_out;
output signed [15:0] u;
input signed [15:0] e_in;
input clk;
input reset;
parameter k1=107;
parameter k2 = 104;
parameter k3 = 2;
reg signed [15:0] u_prev;
reg signed [15:0] e_prev1;
reg signed [15:0] e_prev2;
assign err=(e_in/5);
assign u =(u_prev)+(k1*err)+(k3*e_prev2);
assign u_out = u+(-(k2*e_prev1));
always @ (posedge clk)
if (reset == 1) begin
u_prev <= 0;
e_prev1 <= 0;
e_prev2 <= 0;
end
else begin
e_prev2 <= e_prev1;
e_prev1 <= err;
u_prev <= u_out;
end
endmodule



Code:
module pulse(clk,switches,pwm);
    input clk;
    input [16:0] switches;
    output pwm;
    reg pwm;
    reg [15:0] counter=0;
    parameter sd=195;
    always @ (posedge clk)
    begin
        counter=counter+5;
        if(counter<=switches*sd) pwm=1;
        else pwm=0;
       if (counter>=50000) counter=0;
     end
 endmodule
 

As said before, excepting in/out definitions, the content inside each functional block don´t matter.

You must express it terms of diagram, what exactly do you want connect to what.


+++
 

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