plot gain and phase margin in cadence

[sykab]

ac analysis break loop

Hi!

I’m trying to design, in Cadence, a single-ended CMOS AMPOP and I need to make a ac analysis. Actually, I’m using this schematic as a test bench‘s. Is that right? The problem is that I don’t know what kind of vin should I specify for my analysis:?:

Furthermore, I would like to ask if someone can give me or advice me some kind of information/book about simple single-ended CMOS AMPOP 0,35 µm.

Thanks![/b]

 

[yezeg]

how to do ac analysis of opamp

The input is the nonreverse terminal .The R1 must remove.

 

[yschuang]

opamap ac test setup

In Cadence, you can use stb analysis to do AC simulation.

 

[sykab]

ac analysis example for opamp

The input is the nonreverse terminal .The R1 must remove.

Thanks for your reply. But I have another problem.
The input sinal (vin) should be a vsin. But, I have no idea what amplitude and frequency should I specify


Thanks

 

[pakitos]

ac analysis of op amp

what type of sources do you have?
are you confused bw vsin and vac?
it depends what type of test you want to do.

 

[sykab]

op amp ac analysis

what type of sources do you have?
are you confused bw vsin and vac?
it depends what type of test you want to do.

The voltage supply is 5 V and I want an opamp with a Bandwidth of 100 MHz.
This opamp will be used in a current source with the specifications indicated in the image. I'm thinking to design a simple OTA. Is it a good choice?

Furthermore, I have no idea which amplitude and frequency I should define in the vin (vsin) sinal in the test bench's.

Thanks for your reply.

 

[yschuang]

op amp ac analysis example

Are you trying to get a loop gain plot like bode plot ? If that is what you want, you should add an AC test signal or "iprobe" into the feedback loop. Please refer to the following link.

As for R1, is there any simulation problem like no dc path from your inverting node to gnd if you remove R1. For more details, it is probably helpful to visit
https://www.analog.com/UploadedFiles/Application_Notes/1023068910AN_937.pdf

 

[sykab]

nmos ac analysis, cadence

Are you trying to get a loop gain plot like bode plot ? If that is what you want, you should add an AC test signal or "iprobe" into the feedback loop. Please refer to the following link.

As for R1, is there any simulation problem like no dc path from your inverting node to gnd if you remove R1. For more details, it is probably helpful to visit
https://www.analog.com/UploadedFiles/Application_Notes/1023068910AN_937.pdf

Yes, I'm trying to get a bode plot.

 

[yschuang]

ac op amp

The following link is good for understanding loop gain simulation.
https://www.kenkundert.com/docs/cd2001-01.pdf

 

[ashish_chauhan]

Re: AC analysis of an OPAMP

If you are trying to do an ac analysis, then I dont understand the need of a sine source. Give a DC voltage some where in middle of ICMR and on that ac voltage of 1v. I mean the VIN should be defined like : vinp vin gnd 1.2 ac 1v.

here 1.2 is the dc voltage and 1v is the magnitude of the ac signal.

you dont need to specify the frequency of signal... its job of simulator to sweep the freq and plot the gain and phase.

I cadence environment you can directly use the Y element. no need to specify the ac signal even.

 

[sykab]

Re: AC analysis of an OPAMP

If you are trying to do an ac analysis, then I dont understand the need of a sine source. Give a DC voltage some where in middle of ICMR and on that ac voltage of 1v. I mean the VIN should be defined like : vinp vin gnd 1.2 ac 1v.

here 1.2 is the dc voltage and 1v is the magnitude of the ac signal.

you dont need to specify the frequency of signal... its job of simulator to sweep the freq and plot the gain and phase.

I cadence environment you can directly use the Y element. no need to specify the ac signal even.

At first, thanks for your reply.
It's the first time that I'm using Cadence and I don't know what's "Y element".

 

[ashish_chauhan]

Re: AC analysis of an OPAMP

Hi ,

Y element is just another form of iprobe... or putting more simply its something that trie to implement the middlebrook method of feedback loop analysis, without bothering about the point at which to break the loop. If you dont have Y element with ur suite then go for iprobe, and if even thats not available then refer to the ken kundurts paper metioned earlier in this thread.

 

[dravi99]

Re: AC analysis of an OPAMP

Hi,

You should apply a common mode signal say 1.2v (dc) to the differential pair. it will also have Vin+ and Vin- ac inputs. This common mode signal is necessary to drive the diff. pair and set the voltage Vx, where the tail current source is connected, Typically Nmos. Bias for this nmos will be computed using the simple equation of saturation of transistor Vgs - Vth < Vds.

Thus the Common mode stage sets your voltage Vx, such that current gets divided equally in both arms of the diff pair.

Hope this helps.

 

[tia_design]

Re: AC analysis of an OPAMP

Try Jacob Baker's book, first edition. Also your setup is unity gain set up. Try this way, output is fedback through a big resistor, like 100M to the negative input, then connect a 10uF cap to the negative input.