PLL or DLL what to use for higher frequency then clock pulse

[Ummar]

Hi Every body, i am a new user of FPGA and i am suffering from a basic problem, any one can help please

i am using 16 MHz clock pulse of PCI for my spartan 3 FPGA, it corresponds to cycle time of 62.5 ns. Now i want to generate a pulse of cycle time smaller then this (62.5 ns). some one has told me to use a PLL some other has told me to use DLL, i am confused.

 

[Maxwell077]

Re: PLL or DLL what to use for higher frequency then clock p

In my opinion, DCM is good.. You can create ready-to-use Single DCM by creating IP core source file in Xilinx ISE..

 

[alainsan]

Re: PLL or DLL what to use for higher frequency then clock p

The easiest way to create a higher frequency clock in the Spartan-3 is to use the DCM. The DCM can be configured to generate 16 MHz * M / N, where M and N are integers. Frequencies above 128 MHz can be generated on the Spartan-3 but it may be difficult to meet the timing constraints, depending on the synchronous circuit which follows.

The easiest way to configure the DCM is to use the Wizard in the Core generator. It generates the code automatically.

Note: the DCM is not a true PLL. The resulting clock jitter can be horrendous if M and N are large integers.

Alain Z.
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