mengcy
Member level 5
problem with wander pll
Hi,
I met a problem when simulate the whole loop of PLL. Locking spent about 30us, but after about 80us, Vcrl(the input of VCO) exhibits a ripple about 40mV.and it seems like it will appear again after an amount of time.
my question is: what caused this spur or ripple? Is it possible that it is caused by the simulation tools (Hsim)?
The coefficients are listed below:
Kvco=50M Hz/V,
Icp=20u,
ratio=90,
Fref=4M,
the loop filter is characterized by
Rp=90kHz,
Cp=57.26p,
C1=9.7p
I calculated the loop bandwidth is about 200kHz, and I test the phase margin is 45deg.
Hi,
I met a problem when simulate the whole loop of PLL. Locking spent about 30us, but after about 80us, Vcrl(the input of VCO) exhibits a ripple about 40mV.and it seems like it will appear again after an amount of time.
my question is: what caused this spur or ripple? Is it possible that it is caused by the simulation tools (Hsim)?
The coefficients are listed below:
Kvco=50M Hz/V,
Icp=20u,
ratio=90,
Fref=4M,
the loop filter is characterized by
Rp=90kHz,
Cp=57.26p,
C1=9.7p
I calculated the loop bandwidth is about 200kHz, and I test the phase margin is 45deg.