PLL design in software

[raco_rage]

Hello,

I am designing a PLL on Infineon controller XE164, to counter the jitter produced on CAN bus for some critical applications.

I have made a basic PLL but now I am having problems fine tuning it, which is why I ask your help.

Basically, there is one SYNC pulse train generated by another controller which has to be tracked using the PLL. But the problem is that based on the received SYNC pulse, I need to adjust the timer value for internal control loops.
Ex- if the actual SYNC is delayed, then the duration of each control loop has to be decreased so that they finish off exactly at the same time as the normal SYNC would arrive. There are currently 8 control loops following each SYNC pulse.

The phase difference is calculated as the time difference between the finishing of 8 loops and the arrival of new SYNC pulse. For simpler understanding, you can consider the 8 loops together as 1 internal SYNC or IPSYNC. So, SYNC and IPSYNC should maintain a constant phase ot time difference.

That is all fine and the PLL locks perfectly fine.
But when I have no delay introduced in the SYNC, the IPSYNC is not stable and it has its own jitter.

When I do introduce the jitter on SYNC, IPSYNC jitter is considerably lesser than the SYNC jitter, but the mean value of IPSYNC also deviates.

So the above 2 are my problems, unstable IPSYNC and deviation of mean IPSYNC.

code for the filter is as follows, which is implemented as a 2nd order low pass filter.

*	  Uses discrete time equivalent of a time continuous LPF.
 * 	  y1 = y0 + alpha *(x0 - y0)
 *    try keeping alpha small for a stable filter operation.           	
 *    alpha = t/(RC + t)
 *    t : contstant interval sampling time
*     RC: time constant for the filter
*/
//============================================================================
void IPM_vFilter(long lPhaseDiff)
{
//***********   Low Pass filter   ***********
//*******************************************
//*******************************************
//



    lPhaseDiff	= (lPhaseDiff/IPM_ucIpSyncSubsequenceLimit);
	******************************************************************************
	IPM_liIn_new[0] = lPhaseDiff;

	IPM_liTemp[0] = labs(IPM_liIn_new[0]) - labs(IPM_liOut_old[0]);
		
  	IPM_liTemp[0] >>= 1;                      // alpha = 1/2

  	IPM_liOut_new[0] = IPM_liOut_old[0] + IPM_liTemp[0];

  	IPM_liOut_old[0] = IPM_liOut_new[0];

	IPM_liIn_new[1] = IPM_liOut_new[0];

	IPM_liTemp[1] = labs(IPM_liIn_new[1]) - labs(IPM_liOut_old[1]);
		
  	IPM_liTemp[1] >>= 1;                      // alpha = 1/2

  	IPM_liOut_new[1] = IPM_liOut_old[1] + IPM_liTemp[1];

	IPM_uwNewControlLoopTimerReload = (IPM_uwOldControlLoopTimerReload - (int)IPM_liOut_new[1] - (int)lPhaseDiff);

  	IPM_liOut_old[1] = IPM_liOut_new[1];

	IPM_uwOldControlLoopTimerReload = IPM_uwNewControlLoopTimerReload;

}