PLI in Verilog in which we could model the RAM elements

[m_mosazadeh]

verilog pli

hello all

can anyone help me?

I want to model large memories in verilog.But you know that for modeling for example 1M RAM memory about 32M in system is requierd.

so it will be fine if we could model the RAM elements in PLI.

can anyone help me for writing or finding such PLI?


with very best wishes

 

[vomit]

Re: verilog pli

hello all
I want to model large memories in verilog.But you know that for modeling for example 1M RAM memory about 32M in system is requierd.

You need more memory if you make an array of multi-level logic values. Because each bit needs to hold values for '0', '1', 'X', ... you need more than 1 bit per bit stored. But if you first convert each 32-bit word to an integer, and then store it as an array of integers, you'll get much more memory efficient (and lose the 'X' functionality of course).

That's what I do in VHDL; I can't imagine that Verilog would be much different.

 

[weilijun]

Re: verilog pli

"The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface"
(The Kluwer International Series in Engineering and Computer Science, Volume 666) -- by Stuart Sutherland; Hardcover (Rate it)