Please help me with a problem in lvst:(

[attarzadeh]

Hey everyone
I have got a problem in layout lvs with assura.
when I try to lvs, I get an error that two nets are short circuited, while these nets are the drain and source of my transistor. How is it possible that drain and source short circuited?
Plz help me how to fix it(.

 

[oermens]

you give no useful information. why is it not possible for drain and source to be shorted? where does the short occur, in schematic or layout? give screenshot of the offending device(s).

 

[attarzadeh]

The error in in my layout part.
see, I only use an nmos in schematic and add some port to it. And just instance and nmos in my layout and add port by ctrl+p shortcut and label each metal and poly relatively to the port in schematic
ny drain and source are float how can they become short circuit?
BTW I attached the screen shot

 

[egg]

I think you had wrong set of assura.

check the option of assura.

 

[nsccad]

the rule deck must be review. diffusion area are not define correctly. diffusion area must substract from poly gate. then the source & drain are not shorted.

 

[attarzadeh]

thx nsccad ,
but how can I do it?

 

[nsccad]

poly_gate = geomAnd( poly comp )
diff = geomAndNot( comp poly_gate )

geomConnect(
svia( cont diff poly met1 )
) ;geomConnect

extractMOS(
poly_gate
poly ("G") diff( "S" "D" )
well ("B")
)