Please correct this quartus sysnthesis warnings.....

vasireddyrajesh3 · Oct 23, 2011

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package genlfsr_pkg is
  type T_LFSR_TAPS is array (natural range <>) of integer;
end genlfsr_pkg;







library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.genlfsr_pkg.all;
entity genlfsr is
  generic (
    width  : integer     := 8;      -- number of parallel bits in output
    length : integer     := 8;		-- length of the register
    taps   : T_LFSR_TAPS := (1,2,3,7));
  port (
    rst_n : in  std_logic;
    clk   : in  std_logic;
PI: IN STD_LOGIC_VECTOR(0 TO 31));
end genlfsr;
architecture beh of genlfsr is

signal output : std_logic_vector (0 to 15);
	SIGNAL dout  : std_logic_vector(0 to width-1);
	
	signal clock_count : integer RANGE 0 TO 41:= 0;
	
	signal reg : std_logic_vector(0 to length-1);
	
	signal number : std_logic_vector(0 to 5) :="000000";
	
	type array_encoded_data is array ( 0 to 31 ) of std_logic_vector( 0 to 7);
	
	signal array_encoded_sig : array_encoded_data; 
	
	--signal pi: std_logic_vector(0 to 31):="10101010101010101010101010101010";
	signal binary_data1 : std_logic_vector(0 to 3);
	signal binary_data2 : std_logic_vector(0 to 3);
	signal binary_data3 : std_logic_vector(0 to 3);
	signal binary_data4 : std_logic_vector(0 to 3);
						


	type sum_data_row1 is array (0 to 7)of integer range 0 to 8    ;
	signal sum_data_row_sig1 : sum_data_row1;

	type sum_data_row2 is array (0 to 7)of integer range 0 to 8    ;
	signal sum_data_row_sig2 : sum_data_row2;
	
	type sum_data_row3 is array (0 to 7) of integer range 0 to 8    ;
	signal sum_data_row_sig3 : sum_data_row3;

	type sum_data_row4 is array (0 to 7) of integer range 0 to 8    ;
	signal sum_data_row_sig4 : sum_data_row4;
	
	type serial_data is array (0 to 7) of std_logic_vector(0 to 15);
	signal serial_data_sig : serial_data;
begin  -- beh
------------------------PROCESS STARTS--------------------------------------------------------------------		
		lfsr1 : process (clk,rst_n,BINARY_DATA1,BINARY_DATA2,BINARY_DATA3,BINARY_DATA4,CLOCK_COUNT,OUTPUT)
						variable encoded_data : std_logic;
						variable temp : std_logic_vector(0 to 7);
						variable vreg : std_logic_vector(length-1 downto 0);
						variable fb,sum_temp   : std_logic;
						variable	clock_count_i :integer range 0 to 33 :=0;
						variable sum_data:integer range 0 to 8 :=0;
						
					begin  -- process lfsr1
      
    if rst_n = '0' then                 -- asynchronous reset (active low)
      reg <= (others => '1');
    elsif  clk'EVENT and clk = '1' then  -- rising clock edge
      clock_count<=conv_integer(number);
      number<=number+'1';
		vreg := reg;
      for i in 1 to width loop
        fb := '0';
        for j in taps'range loop
          if fb=vreg(taps(j)-1) then
            fb := '0';
          else
            fb := '1';
          end if;
        end loop;  -- j
        for k in vreg'left downto 1  loop
          vreg(k) := vreg(k-1);
        end loop;  -- k
        vreg(0) := fb;
      end loop;  -- i
      reg <= vreg;
    end if;   
  dout <= reg(0 to width-1);
----------------LFSR END------------------------------------------------------------------------------
  
  
  
-----------------------------
  if clock_count=1 then
	for i in 0 to 7 loop
	temp(i):= dout(i) xor pi(0);
	array_encoded_sig(0)<=temp;
	end loop;
------------------------------	
------------------------------	 	 
	 elsif clock_count=2 then
	 for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(1);
		array_encoded_sig(1)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count=3 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(2);
		array_encoded_sig(2)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	
	elsif clock_count= 4 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(3);
		array_encoded_sig(3)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 5 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(4);
		array_encoded_sig(4)<=temp;
	end loop;
--------------------------------	
--------------------------------	
	elsif clock_count= 6 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(5);
		array_encoded_sig(5)<=temp;
	end loop;
---------------------------------
---------------------------------	
	elsif clock_count= 7 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(6);
		array_encoded_sig(6)<=temp;
	end loop;
---------------------------------
---------------------------------	
	elsif clock_count= 8 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(7);
		array_encoded_sig(7)<=temp;
	end loop;
-----------------------------------	
-----------------------------------	
  elsif clock_count=9 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(8);
		array_encoded_sig(8)<=temp;
	end loop;
-----------------------------------
-----------------------------------	 	 
	 elsif clock_count=10 then
	 for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(9);
		array_encoded_sig(9)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count=11 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(10);
		array_encoded_sig(10)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 12 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(11);
		array_encoded_sig(11)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 13 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(12);
		array_encoded_sig(12)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 14 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(13);
		array_encoded_sig(13)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 15 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(14);
		array_encoded_sig(14)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 16 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(15);
		array_encoded_sig(15)<=temp;
	end loop;
-------------------------------	
-------------------------------		
  elsif clock_count=17 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(16);
		array_encoded_sig(16)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	 elsif clock_count=18 then
	 for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(17);
		array_encoded_sig(17)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count=19 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(18);
		array_encoded_sig(18)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 20 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(19);
		array_encoded_sig(19)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 21 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(20);
		array_encoded_sig(20)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	
	elsif clock_count= 22 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(21);
		array_encoded_sig(21)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 23 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(22);
		array_encoded_sig(22)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count=24 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(23);
		array_encoded_sig(23)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	
	
  elsif clock_count=25 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(24);
		array_encoded_sig(24)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	 elsif clock_count=26 then
	 for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(25);
		array_encoded_sig(25)<=temp;
	end loop;
-------------------------------	
-------------------------------		

	elsif clock_count=27 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(26);
		array_encoded_sig(26)<=temp;
	end loop;
	
-------------------------------	
-------------------------------		
	
	elsif clock_count= 28 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(27);
		array_encoded_sig(27)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 29 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(28);
		array_encoded_sig(28)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	
	elsif clock_count= 30 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(29);
		array_encoded_sig(29)<=temp;
	end loop;
-------------------------------	
-------------------------------	
	elsif clock_count= 31 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(30);
		array_encoded_sig(30)<=temp;
	end loop;
-------------------------------	
-------------------------------		
	elsif clock_count= 32 then
	for i in 0 to 7 loop
		temp(i):= dout(i) xor pi(31);
		array_encoded_sig(31)<=temp;
	end loop;
	end if;
-------------------------------	
-------------------------------		
	
	----------------------------------------------------------------------
	---------------------------------------------------------------------
	---------------------------summing of arrays--------------------------
	----------------------------------------------------------------------
	----------------------------------------------------------------------
	
	----------------------------------------------------
	sum_data:=0;
	for i in 0 to 7 loop
			sum_temp:=array_encoded_sig(i)(0);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(0)<=sum_data;
	end loop;
		------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(1);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(1)<=sum_data;
	end loop;
		-------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(2);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(2)<=sum_data;
	end loop;
		--------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(3);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(3)<=sum_data;
	end loop;
		
		---------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(4);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(4)<=sum_data;
	end loop;
		
		----------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(5);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(5)<=sum_data;
	end loop;
		
		-----------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(6);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(6)<=sum_data;
	end loop;
		
		------------------------------------------------------
		sum_data:=0;
	for i in 0 to 7 loop
		sum_temp:=array_encoded_sig(i)(7);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig1(7)<=sum_data;
	end loop;
		
--------------sum_data_row2---------------------------	
		
------------------------------------------------------
	sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(0);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(0)<=sum_data;
	end loop;
-------------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(1);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(1)<=sum_data;
	end loop;
---------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(2);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(2)<=sum_data;
	end loop;
		----------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(3);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(3)<=sum_data;
	end loop;
		
		------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(4);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(4)<=sum_data;
	end loop;
		
---------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(5);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(5)<=sum_data;
	end loop;
		
------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(6);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(6)<=sum_data;
	end loop;
		
		-----------------------------------------------------
		sum_data:=0;
	for i in 8 to 15 loop
		sum_temp:=array_encoded_sig(i)(7);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig2(7)<=sum_data;
	end loop;
	
------sum_data_rows3-----------------------------------------
-------------------------------------------------------------
	sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(0);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(0)<=sum_data;
	end loop;
---------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(1);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(1)<=sum_data;
	end loop;
---------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(2);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(2)<=sum_data;
	end loop;
--------------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(3);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(3)<=sum_data;
	end loop;
		
--------------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(4);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(4)<=sum_data;
	end loop;
		
--------------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(5);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(5)<=sum_data;
	end loop;
		
--------------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(6);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(6)<=sum_data;
	end loop;
		
-------------------------------------------------------------
		sum_data:=0;
	for i in 16 to 23 loop
		sum_temp:=array_encoded_sig(i)(7);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig3(7)<=sum_data;
	end loop;
		
-----------sum_data_rows4------------------------------------
	
------------------------------------------------------------
	sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(0);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(0)<=sum_data;
	end loop;
------------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(1);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(1)<=sum_data;
	end loop;
-----------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(2);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(2)<=sum_data;
	end loop;
--------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(3);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(3)<=sum_data;
	end loop;
		
-----------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(4);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(4)<=sum_data;
	end loop;
		
--------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(5);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(5)<=sum_data;
	end loop;
		
-------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(6);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(6)<=sum_data;
	end loop;
		
--------------------------------------------------------
		sum_data:=0;
	for i in 24 to 31 loop
		sum_temp:=array_encoded_sig(i)(7);
	if(sum_temp='1')then
		sum_data:=sum_data+1;
	end if;
		sum_data_row_sig4(7)<=sum_data;
	end loop;
		
	if clock_count=33 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(0),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(0),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(0),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(0),4);	
	end if;
		
		
	if clock_count=34 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(1),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(1),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(1),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(1),4);	
  
	end if;
		
	if clock_count=35 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(2),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(2),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(2),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(2),4);	
  	end if;
		
	
	if clock_count=36 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(3),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(3),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(3),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(3),4);	
	end if;
	if clock_count=37 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(4),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(4),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(4),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(4),4);	
  	end if;
		
	if clock_count=38 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(5),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(5),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(5),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(5),4);	
	end if;
		
	if clock_count=39 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(6),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(6),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(6),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(6),4);	
	end if;
		
	if clock_count=40 then
	binary_data1<=conv_std_logic_vector(sum_data_row_sig1(7),4);
  binary_data2<=conv_std_logic_vector(sum_data_row_sig2(7),4);	
	binary_data3<=conv_std_logic_vector(sum_data_row_sig3(7),4);	
  binary_data4<=conv_std_logic_vector(sum_data_row_sig4(7),4);	
	end if;
	
	
	output<=((binary_data1) & (binary_data2) & (binary_data3) & (binary_data4));
	
	if clock_count=34 then
	serial_data_sig(0)<=output;
	
	elsif clock_count=35 then
	serial_data_sig(1)<=output;
	
	elsif clock_count=36 then
	serial_data_sig(2)<=output;

	elsif clock_count=37 then
	serial_data_sig(3)<=output;
	
	elsif clock_count=38 then
	serial_data_sig(4)<=output;
	
	elsif clock_count=37 then
	serial_data_sig(5)<=output;
	
	elsif clock_count=39 then
	serial_data_sig(5)<=output;
	
	elsif clock_count=40 then
	serial_data_sig(6)<=output;
	
	elsif clock_count=41 then
	serial_data_sig(7)<=output;
	end if;
		
	end process;
	
	end beh;

THESE ARE THE WARNINGS

Code:

Warning: Parallel compilation is not licensed and has been disabled
Warning (10036): Verilog HDL or VHDL warning at genlfsr.VHD(68): object "serial_data_sig" assigned a value but never read
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(103): signal "reg" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(111): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(111): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(118): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(118): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(125): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(125): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(133): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(133): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(140): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(140): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(147): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(147): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(154): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(154): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(161): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(161): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(168): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(168): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(175): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(175): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(182): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(182): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(189): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(189): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(196): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(196): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(203): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(203): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(210): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(210): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(217): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(217): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(224): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(224): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(231): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(231): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(238): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(238): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(245): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(245): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(252): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(252): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(260): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(260): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(267): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(267): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(274): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(274): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(283): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(283): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(290): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(290): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(298): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(298): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(307): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(307): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(314): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(314): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(322): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(322): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(329): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(329): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(336): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(336): signal "PI" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(352): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(361): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(370): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(379): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(389): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(399): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(409): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(419): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(431): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(440): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(449): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(458): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(468): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(478): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(488): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(498): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(509): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(518): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(527): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(536): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(546): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(556): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(566): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(576): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(588): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(597): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(606): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(615): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(625): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(635): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(645): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(655): signal "array_encoded_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(663): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(664): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(665): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(666): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(671): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(672): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(673): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(674): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(679): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(680): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(681): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(682): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(687): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(688): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(689): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(690): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(693): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(694): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(695): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(696): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(700): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(701): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(702): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(703): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(707): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(708): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(709): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(710): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(714): signal "sum_data_row_sig1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(715): signal "sum_data_row_sig2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(716): signal "sum_data_row_sig3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at genlfsr.VHD(717): signal "sum_data_row_sig4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "temp", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "array_encoded_sig", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "binary_data1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "binary_data2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "binary_data3", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at genlfsr.VHD(71): inferring latch(es) for signal or variable "binary_data4", which holds its previous value in one or more paths through the process
Warning: Entity "genlfsr" contains only dangling pins
Warning: Design contains 34 input pin(s) that do not drive logic
	Warning (15610): No output dependent on input pin "rst_n"
	Warning (15610): No output dependent on input pin "clk"
	Warning (15610): No output dependent on input pin "PI[31]"
	Warning (15610): No output dependent on input pin "PI[30]"
	Warning (15610): No output dependent on input pin "PI[29]"
	Warning (15610): No output dependent on input pin "PI[28]"
	Warning (15610): No output dependent on input pin "PI[27]"
	Warning (15610): No output dependent on input pin "PI[26]"
	Warning (15610): No output dependent on input pin "PI[25]"
	Warning (15610): No output dependent on input pin "PI[24]"
	Warning (15610): No output dependent on input pin "PI[23]"
	Warning (15610): No output dependent on input pin "PI[22]"
	Warning (15610): No output dependent on input pin "PI[21]"
	Warning (15610): No output dependent on input pin "PI[20]"
	Warning (15610): No output dependent on input pin "PI[19]"
	Warning (15610): No output dependent on input pin "PI[18]"
	Warning (15610): No output dependent on input pin "PI[17]"
	Warning (15610): No output dependent on input pin "PI[16]"
	Warning (15610): No output dependent on input pin "PI[15]"
	Warning (15610): No output dependent on input pin "PI[14]"
	Warning (15610): No output dependent on input pin "PI[13]"
	Warning (15610): No output dependent on input pin "PI[12]"
	Warning (15610): No output dependent on input pin "PI[11]"
	Warning (15610): No output dependent on input pin "PI[10]"
	Warning (15610): No output dependent on input pin "PI[9]"
	Warning (15610): No output dependent on input pin "PI[8]"
	Warning (15610): No output dependent on input pin "PI[7]"
	Warning (15610): No output dependent on input pin "PI[6]"
	Warning (15610): No output dependent on input pin "PI[5]"
	Warning (15610): No output dependent on input pin "PI[4]"
	Warning (15610): No output dependent on input pin "PI[3]"
	Warning (15610): No output dependent on input pin "PI[2]"
	Warning (15610): No output dependent on input pin "PI[1]"
	Warning (15610): No output dependent on input pin "PI[0]"
	Warning (15610): No output dependent on input pin "rst_n"
	Warning (15610): No output dependent on input pin "clk"
	Warning (15610): No output dependent on input pin "PI[31]"
	Warning (15610): No output dependent on input pin "PI[30]"
	Warning (15610): No output dependent on input pin "PI[29]"
	Warning (15610): No output dependent on input pin "PI[28]"
	Warning (15610): No output dependent on input pin "PI[27]"
	Warning (15610): No output dependent on input pin "PI[26]"
	Warning (15610): No output dependent on input pin "PI[25]"
	Warning (15610): No output dependent on input pin "PI[24]"
	Warning (15610): No output dependent on input pin "PI[23]"
	Warning (15610): No output dependent on input pin "PI[22]"
	Warning (15610): No output dependent on input pin "PI[21]"
	Warning (15610): No output dependent on input pin "PI[20]"
	Warning (15610): No output dependent on input pin "PI[19]"
	Warning (15610): No output dependent on input pin "PI[18]"
	Warning (15610): No output dependent on input pin "PI[17]"
	Warning (15610): No output dependent on input pin "PI[16]"
	Warning (15610): No output dependent on input pin "PI[15]"
	Warning (15610): No output dependent on input pin "PI[14]"
	Warning (15610): No output dependent on input pin "PI[13]"
	Warning (15610): No output dependent on input pin "PI[12]"
	Warning (15610): No output dependent on input pin "PI[11]"
	Warning (15610): No output dependent on input pin "PI[10]"
	Warning (15610): No output dependent on input pin "PI[9]"
	Warning (15610): No output dependent on input pin "PI[8]"
	Warning (15610): No output dependent on input pin "PI[7]"
	Warning (15610): No output dependent on input pin "PI[6]"
	Warning (15610): No output dependent on input pin "PI[5]"
	Warning (15610): No output dependent on input pin "PI[4]"
	Warning (15610): No output dependent on input pin "PI[3]"
	Warning (15610): No output dependent on input pin "PI[2]"
	Warning (15610): No output dependent on input pin "PI[1]"
	Warning (15610): No output dependent on input pin "PI[0]"
Warning: Parallel compilation is not licensed and has been disabled
Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning: No clocks defined in design.
Warning: Parallel compilation is not licensed and has been disabled
Warning: No clocks defined in design.
Warning: No clocks defined in design.
Warning: No clocks defined in design.
Warning: Device family does not support board-level Boundary-Scan Description Language file generation
Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER

FvM · Oct 23, 2011

I mainly restrict my answer to the most obvious point. Looking at the port definition, the design has only inputs but no outputs. That means, it will be reduced to nothing in synthesis, because it doesn't present a reasonable logic hardware.

Code:

  port (
    rst_n : in  std_logic;
    clk   : in  std_logic;
PI: IN STD_LOGIC_VECTOR(0 TO 31));

Circuits without outputs are only meaningful as simulation testbench.

You should solve this problem respectively become clear about the purpose of your design first.

You have many warnings about missing entries in sensitivity lists. They are meaningless for synthesis as such but must be considered to achieve consistent simulation. They may also indicate elementary weaknesses of the design structure, because you ususally don't have much combinational processes in a FPGA design. It's the same with the "inferring latches" warning.

vasireddyrajesh3 · Oct 27, 2011

Is it necessary to mention all signals used in vhdl program ,in process sensitivity list?
because , without providing signals simulation is done.. but without signal representation in process ,syntheses is not possible,getting errors..
another error is

Code:

Warning (10631): VHDL Process Statement warning at CDMA_ENCODING_PHASE_1_REVIEW.VHD(69): inferring latch(es) for signal or variable "binary_data1", which holds its previous value in one or more paths through the process

kindly help regarding this..

thanks and regards,
Rajesh.

TrickyDicky · Oct 27, 2011

Correct sensitivity list necessary for simulation, because synthesis ignores sensitivity lists, and if you get the list incorrect you will get a missmatch between synthesis and simulation results.

Looking at that warning, the errors are probably because of your poor logic description. But did you follow FvM's point? without outputs, you will get nothing out of synthesis.

FvM · Oct 27, 2011

Strictly spoken, there's not a single error in the quoted report, but a mass of warnings. In some cases, warnings in fact indicate a serious problem, but they may also be brought up by intentional design features. I already gave a detailed comment about the warnings in your report.

But as long as the design is effectively functionless, I can't determine if the problems reflected in the warnings affect the design operation. In addition, I'm not sure if I'll understand the intended function.

vasireddyrajesh3 · Nov 11, 2011

Dear FvM,

As per your advice i edited my program by giving output ports, i reduced some warnings,but still it has some errors on sensitivity lists. Again i kept all my signals used in the program. but still its getting warnings... actually the program is about Encoding(XOR) of 32-bit data with 8-bit data .That means, at each bit of 32-bit data , i have to encode with 8-bit different code for each bit.

for example:
32-bit data is say D₀-D₃₁

8-bit data is say C_0-C₇

NOW
D₀ has to XOR with C₀-C₇ then
D₁ has to XOR with C₀-C₇now 8-bit code is different than firstone..

like that i have to do it for 32-bits with different 8-bit codes by taking each bit of 32-bit at a time .

for this please give me some other logic..

other wise i got an idea of reversible logic,means.. 32-bit data is converted into 8-bit data again if i do the same process the same 32-bit we will get, is there any logic . we can use any logic in between , main aim is to encoded data has to be sent through the AVALON BUS. simillarly at slave side i have to decode it and get the same 32-bit data.

this is my project.. please help.

FvM · Nov 11, 2011

The sensitivity list warnings are issued, because many input signals to the combinational part of the process are not listed. This may lead to simulation mismatch, but doesn't prevent correct synhesis.

I doubt however, that it's a good idea to have so much combinational respectively asynchronous code.

The more serious warnings are all "No output dependent on input pin xxx" which means that all of your logic is ignored in synthesis. I already addresed the problem previously. I don't know if you corrected it.

For the other problem, I don't know what you exactly want to achieve. A clear specification of the intended algorithm would be helpful.

vasireddyrajesh3 · Nov 11, 2011

Code:

lfsr1 : process (clk,rst_n,BINARY_DATA1,BINARY_DATA2,BINARY_DATA3,BINARY_DATA4,CLOCK_COUNT,OUTPUT,PI,array_encoded_sig,dout,sum_data_row_sig1,sum_data_row_sig2,sum_data_row_sig3,sum_data_row_sig4)

i edited my signals like this.. again , some warnings are there
Thanks for reply .

FvM · Nov 11, 2011

You should try to understand the reason for the warnings yourself, referring to VHDL rules. The more interesting question is, if the design is working now.

vasireddyrajesh3 · Nov 15, 2011

Code:

for i in 0 to 7 loop
	temp(i):= dout(i) xor pi(clock_count);
	array_encoded_sig(clock_count)<=temp;
	end loop;

Code:

temp

is vector of 0 to 7

Code:

array_encoded_sig

is the array signal of 32X8 array.

Code:

clock_count

is the clock count.

i have a problem here... after the clock_count=32. count is not increasing....
any body kindly help.

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Please correct this quartus sysnthesis warnings.....

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