adam_lo
Newbie level 6
Hello,
Please, I need help so much.
I don't now why when I add my custom ip core .this error appeared.
what this error mean?
and how to solve it ?
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 108
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 22 sec
Total CPU time to NGDBUILD completion: 21 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 12.1 - Map M.53d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <E:/ISSe/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda>
with local file <E:/ISSe/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "3sd3400afg676-4".
Mapping design into LUTs...
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol
"physical_group_clk_125_0000MHzDCM0/clock_generator_0/clock_generator_0/DCM0_
CLK0_BUFG_INST" (output signal=clk_125_0000MHzDCM0) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin I0 of
DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/infrastructur
e/cal_top/tap_dly/gen_no_sim.l0
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
ERROR
ack:1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the constraint. A timing constraint summary
below shows the failing constraints (preceded with an Asterisk (*)). Please
use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
PCF files to identify which constraints and paths are failing because of the
component delays alone. If the failing path(s) is mapped to Xilinx components
as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing
the path. To allow the tools to bypass this error, set the environment
variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference manual; for more information on TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -1.864ns| 17.864ns| 19| 16212
G_DCM0_CLKDV = PERIOD TIMEGRP "clock_gene | HOLD | 0.134ns| | 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLKDV" | | | | |
TS_sys_clk_pin / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<7>" MAXDELAY = 0.53 | | | | |
ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<15>" MAXDELAY = 0.5 | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<23>" MAXDELAY = 0.5 | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<0>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<1>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<2>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<3>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_SI | SETUP | 1.835ns| 4.869ns| 0| 0
G_DCM0_CLK0 = PERIOD TIMEGRP "clock_gener | HOLD | 0.438ns| | 0| 0
ator_0_clock_generator_0_SIG_DCM0_CLK0" T | | | | |
S_sys_clk_pin HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<3>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<2>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<1>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<0>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<3>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<0>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<1>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<2>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_SI | SETUP | 2.578ns| 2.844ns| 0| 0
G_DCM0_CLK90 = PERIOD TIMEGRP "clock_gene | HOLD | 0.552ns| | 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLK90" | MINLOWPULSE | 5.036ns| 2.964ns| 0| 0
TS_sys_clk_pin PHASE 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/rst_dqs_div" MAXDELAY = | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay2" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay1" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay4" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay3" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay5" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP | 7.006ns| 0.994ns| 0| 0
pin" 125 MHz HIGH 50% | HOLD | 0.704ns| | 0| 0
| MINLOWPULSE | 3.200ns| 4.800ns| 0| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_sys_clk_pin | 8.000ns| 4.800ns| 8.932ns| 0| 19| 3|
492225|
| TS_clock_generator_0_clock_gen| 8.000ns| 4.869ns| N/A| 0| 0| 5422|
0|
| erator_0_SIG_DCM0_CLK0 | | | | | | |
|
| TS_clock_generator_0_clock_gen| 8.000ns| 2.964ns| N/A| 0| 0| 980|
0|
| erator_0_SIG_DCM0_CLK90 | | | | | | |
|
| TS_clock_generator_0_clock_gen| 16.000ns| 17.864ns| N/A| 19| 0| 485823|
0|
| erator_0_SIG_DCM0_CLKDV | | | | | | |
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
1 constraint not met.
Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.
Please, Realy I need your help so..... much
thanks in advance
Regards
Adam
Please, I need help so much.
I don't now why when I add my custom ip core .this error appeared.
what this error mean?
and how to solve it ?
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 108
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 22 sec
Total CPU time to NGDBUILD completion: 21 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 12.1 - Map M.53d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <E:/ISSe/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda>
with local file <E:/ISSe/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "3sd3400afg676-4".
Mapping design into LUTs...
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol
"physical_group_clk_125_0000MHzDCM0/clock_generator_0/clock_generator_0/DCM0_
CLK0_BUFG_INST" (output signal=clk_125_0000MHzDCM0) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin I0 of
DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/infrastructur
e/cal_top/tap_dly/gen_no_sim.l0
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
ERROR
ack:1653 - At least one timing constraint is impossible to meet becausecomponent delays alone exceed the constraint. A timing constraint summary
below shows the failing constraints (preceded with an Asterisk (*)). Please
use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
PCF files to identify which constraints and paths are failing because of the
component delays alone. If the failing path(s) is mapped to Xilinx components
as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing
the path. To allow the tools to bypass this error, set the environment
variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference manual; for more information on TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -1.864ns| 17.864ns| 19| 16212
G_DCM0_CLKDV = PERIOD TIMEGRP "clock_gene | HOLD | 0.134ns| | 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLKDV" | | | | |
TS_sys_clk_pin / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[1]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col0/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay4" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[3]..u_dqs_delay | | | | |
_col1/delay2" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay5" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[0]..u_dqs_delay | | | | |
_col0/delay1" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.090ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/gen_dqs[2]..u_dqs_delay | | | | |
_col0/delay3" MAXDELAY = 0.19 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<7>" MAXDELAY = 0.53 | | | | |
ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<15>" MAXDELAY = 0.5 | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.430ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/infrastructur | | | | |
e/cal_top/tap_dly/tap<23>" MAXDELAY = 0.5 | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<0>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<1>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<2>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 0.600ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/dqs_int_delay | | | | |
_in<3>" MAXDELAY = 0.7 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_SI | SETUP | 1.835ns| 4.869ns| 0| 0
G_DCM0_CLK0 = PERIOD TIMEGRP "clock_gener | HOLD | 0.438ns| | 0| 0
ator_0_clock_generator_0_SIG_DCM0_CLK0" T | | | | |
S_sys_clk_pin HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<3>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<2>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<1>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_1_wr_en<0>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<3>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<0>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<1>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 1.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/fif | | | | |
o_0_wr_en<2>" MAXDELAY = 2 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_SI | SETUP | 2.578ns| 2.844ns| 0| 0
G_DCM0_CLK90 = PERIOD TIMEGRP "clock_gene | HOLD | 0.552ns| | 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLK90" | MINLOWPULSE | 5.036ns| 2.964ns| 0| 0
TS_sys_clk_pin PHASE 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/rst_dqs_div" MAXDELAY = | | | | |
3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay2" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay1" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay4" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay3" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/ge | MAXDELAY | 2.900ns| 0.100ns| 0| 0
n_s3_ddr2_phy.mpmc_phy_if_0/data_path/dat | | | | |
a_read_controller/.rst_dqs_div_delayed/de | | | | |
lay5" MAXDELAY = 3 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP | 7.006ns| 0.994ns| 0| 0
pin" 125 MHz HIGH 50% | HOLD | 0.704ns| | 0| 0
| MINLOWPULSE | 3.200ns| 4.800ns| 0| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_sys_clk_pin | 8.000ns| 4.800ns| 8.932ns| 0| 19| 3|
492225|
| TS_clock_generator_0_clock_gen| 8.000ns| 4.869ns| N/A| 0| 0| 5422|
0|
| erator_0_SIG_DCM0_CLK0 | | | | | | |
|
| TS_clock_generator_0_clock_gen| 8.000ns| 2.964ns| N/A| 0| 0| 980|
0|
| erator_0_SIG_DCM0_CLK90 | | | | | | |
|
| TS_clock_generator_0_clock_gen| 16.000ns| 17.864ns| N/A| 19| 0| 485823|
0|
| erator_0_SIG_DCM0_CLKDV | | | | | | |
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
1 constraint not met.
Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.
Please, Realy I need your help so..... much
thanks in advance
Regards
Adam