Pipeline Vs Sequential

[vimalk]

Hi,

I have a basic doubt. In VHDL all process are concurrent, i agree, but what about the statements in all these processes. Are they sequential or concurrent or pipelined ?

 

[dpaul]

From what I understand, all statements inside a process are executed sequentially.

The signal assignment (<=) is performed after all the sequential code in the processes are done executing. This is when all the active processes for that time-step are done.
The variable assignment =) executes immediately and can be used, for e.g. to temporarily store some data inside a process.

 

[xtcx]

Hi,

I have a basic doubt. In VHDL all process are concurrent, i agree, but what about the statements in all these processes. Are they sequential or concurrent or pipelined ?

> All process are concurrent
> Statements inside process can be concurrent or sequential depends upon your modeling.For eg

process(a,b)
begin
 c <= a xor b;
end process;

process(x,y)
begin
z <= x xor y;
end process;

process(clk)
begin

if rising_edge(clk) then
    m <= n xor o;
end if;

end process;

-- here m outputs are sequential or timed (as referred by clock); whereas first two process work at same unit time.
> Multiple sequential logic can lead to a pipelined design (but not limited to). But pipeline is much toward staging your outputs such a way that you can add up more parallelism to your logic. For example, we pipeline a path if the time between two sequential logic in that path is very high. However pipeline concept of a processor is different, for eg use output early for the next process to start early.

In VHDL, <= is sequential and := is concurrent. But it depends on how you apply

 

[TrickyDicky]

In VHDL, <= is sequential and := is concurrent. But it depends on how you apply

Both <= and := are sequential. All of VHDL is basically sequential. using a signal assignment (<=) just schedules a signal to be updated at the end of the current delta.

 

[xtcx]

Both <= and := are sequential. All of VHDL is basically sequential. using a signal assignment (<=) just schedules a signal to be updated at the end of the current delta.

Thanks for the correction. By concurrent I assume assignments on RHS will appear on LHS with just wire delay whereas by sequential, RHS will be scheduled to assign to LHS at x time + wire delay. On hardware := is nothing more than wire

 

[TrickyDicky]

Thanks for the correction. By concurrent I assume assignments on RHS will appear on LHS with just wire delay whereas by sequential, RHS will be scheduled to assign to LHS at x time + wire delay. On hardware := is nothing more than wire

This is still incorrect. The sequential order of := assignments can affect whether the variable is turned into a wire or a register.

process(clk)
  variable a, b : std_logic;
begin
  if rising_edge(clk) then
    a := ip;
    op1 <= a;
 
    op2 <= b;
    b := ip;
    
  end if;
end process;

Here, a is a wire, b is a register.

 

[wtr]

In VHDL all process are concurrent, i agree,

Good

but what about the statements in all these processes. Are they sequential or concurrent or pipelined ?

A process is a sequence of statements. Executed in the specified order (thus sequential).

A Process can have values in the sensitivity list making it combinatorial or synchronous
A Process can have NO values in the sensitivity list making it sequential (wait statements etc).

You can have a combinatorial process that appears to acts concurrently

---

Code VHDL - [expand]
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process(x,y)
begin
z <= x xor y;
end process;
-- similar to concurrent signal assignment
z <= x xor y; -- in the architecture level
-- maybe even synthesises to same

---

What you should do is consider something concurrent if it sits within the architecture body & sequential if it sits within a process (or represents a logic circuit that includes storage elements).

Regarding Pipelines - "A pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one". This is normally done by registering the output element on a synchronous process.

Hope this helps