promach
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wReady[0] = ~rValid[1] | wReady[1]
wReady[0] = ~$past(_rValid[1]) | wReady[1]
wReady[0] = ~$past(rValid[0] | (rValid[1] & ~wReady[1])) | wReady[1]
wReady[0] = $past(~rValid[0] & (~rValid[1] | wReady[1])) | wReady[1]
WR_DATA_READY = $past(~WR_DATA_VALID & (~RD_DATA_VALID | RD_DATA_READY)) | RD_DATA_READY
For pipeline, do you guys have any comments about the above expression for WR_DATA_READY which is derived from line 40 and 59 of the following verilog code or reg_pipeline.v ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 module reg_pipeline #( parameter C_DEPTH = 1, parameter C_WIDTH = 128 ) ( input CLK, input RST_IN, input [C_WIDTH-1:0] WR_DATA, input WR_DATA_VALID, output WR_DATA_READY, output [C_WIDTH-1:0] RD_DATA, output RD_DATA_VALID, input RD_DATA_READY ); genvar i; wire wReady [C_DEPTH:0]; reg [C_WIDTH-1:0] _rData [C_DEPTH:1], rData [C_DEPTH:0]; reg _rValid [C_DEPTH:1], rValid [C_DEPTH:0]; // Read interface assign wReady[C_DEPTH] = RD_DATA_READY; assign RD_DATA = rData[C_DEPTH]; assign RD_DATA_VALID = rValid[C_DEPTH]; // Write interface assign WR_DATA_READY = wReady[0]; always @(*) begin rData[0] = WR_DATA; rValid[0] = WR_DATA_VALID; end generate for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages assign #1 wReady[i-1] = ~rValid[i] | wReady[i]; // Data Registers always @(*) begin _rData[i] = rData[i-1]; end // Enable the data register when the corresponding stage is ready always @(posedge CLK) begin if(wReady[i-1]) begin rData[i] <= #1 _rData[i]; end end // Valid Registers always @(*) begin if(RST_IN) begin _rValid[i] = 1'b0; end else begin _rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]); end end // Always enable the valid registers always @(posedge CLK) begin rValid[i] <= #1 _rValid[i]; end end endgenerate endmodule
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