Pipeline architecture

[p11]

actually simply what i need is if i need to send data from 1 block to another then simple parallel transfer is not possible as there is lack of resource. Serial transfer is not possible as it needs time.. Now is there any other way to transfer the data . Someone told me to use pipeline architecture .. From net search i found that it implies transfer of data bt not all at a time. say if i have 100 data to transfer , and if i transfer 10 at a time , then after sending data 10 times all data will be send. Is this a pipeline architecture...???

 

[dpaul]

What you need is a combination of serial and parallel data transfer. I will illustrate this with the help of a simple example.

Suppose you have a 8 bit register and you want to transfer all these 8 bits. Now lets say due to resource constraints, you cannot use a 8bit wide o/p port. So what do you do?
Assuming that a 4 bits o/p port is feasible, you can then transfer the 8 bits data in two clock cycles rather than in 1 clk cycle. In the 1st clk cycle you transfer 4 bits and then in the next another 4 bits. If you want to use lesser resources, then use a 2 bits o/p port and transfer your 8 bits data in 4 clock cycles.

In such cases, it is always a compromise b/w latency and resource usage.

 

[xtcx]

actually simply what i need is if i need to send data from 1 block to another then simple parallel transfer is not possible as there is lack of resource. Serial transfer is not possible as it needs time.. Now is there any other way to transfer the data . Someone told me to use pipeline architecture .. From net search i found that it implies transfer of data bt not all at a time. say if i have 100 data to transfer , and if i transfer 10 at a time , then after sending data 10 times all data will be send. Is this a pipeline architecture...???

That is what close to burst transfer, as Continuous transfer (Parallel or Serial) on a bus will hold the bus for longer time in a Multilayer bus system like AHB or AXI. So Rather than writing all your 100 data, set 10 as your burst size and send it 10 times at certain period so that the bus will not be put on hold. I usually set 128 bytes. As far as I know, a pipe architecture is that data is processed in stages so that multicycle can be avoided for a single data processing, be it an Instruction decode or a DSP multiplier. Could you share the webpage that showed about this?.

 

[TrickyDicky]

A pipeline is simple a chain of registers with logic in between to process the data in some way over a period of several clock cycles. The more pipelining there is, the amount of logic between pipe stages can be reduced which will increase the potential clock speed of the pipeline, increasing the throughput.

What the OP is talking about would be muxing and de-muxing a data path. This can be done in a pipeline. Serialising the data is just the same.

@OP: please be more specific about what you're trying to do.

 

[p11]

Actually am trying to send lots of data say more than 1000 from one memory to another within a specific period of time... but just simply transferring the data causes resource shortage ..serial transfer takes more time ... so any idea .. please help/

 

[TrickyDicky]

Well, you can only transfer data as fast as the clock. If you have 1000 words to transfer, it will take 1000 clocks minimum.

 

[bking]

Actually am trying to send lots of data say more than 1000 from one memory to another within a specific period of time/

What is the specific period of time allowed? Exactly how many bits need to move in that time?

 

[p11]

next data set will come after 100 ns. so i need to transfer this data within 100ns ....

 

[TrickyDicky]

next data set will come after 100 ns. so i need to transfer this data within 100ns ....

Without the specification of the system, its impossible to help. Whats the clock speed? whats the bus size? is that 1000 words or 1000 bits? whats the memory bus size?

 

[p11]

i am trying to implement it in FPGA(spartan 3E).right now just checking in vhdl testbench.Am using 9.1 xilinx. now what i need is that if i design a system where after every 100ns am getting a huge amount of data, consider 1000,then how to store it . i cant use simple parallel or serial transfer .Right now i am using 20 bit data.. may vary later ...

 

[srizbf]

In the first 100ns , a data set is received .
Put it in a buffer as you receive.

For the next 100ns form or point to a separate buffer to receive next set of data in the next 100ns.

When you are receiving 2nd set of data , you can process 1st set in the first buffer and clear it or whatever you want to do.

In the 3rd slot , point to the first buffer if possible or a separate buffer. repeats for ever...

dont know whether it meets your requirement. But this is one possible solution.

 

[TrickyDicky]

i am trying to implement it in FPGA(spartan 3E).right now just checking in vhdl testbench.Am using 9.1 xilinx. now what i need is that if i design a system where after every 100ns am getting a huge amount of data, consider 1000,then how to store it . i cant use simple parallel or serial transfer .Right now i am using 20 bit data.. may vary later ...

Why such an old ISE version?
What is your clock speed?
How can your data width "vary later"?
1000 what? bits or words? 20 bits per word?
What are the interfaces you're using?
You still have not answered these questions from earlier - without more details we cannot do anything more than guess.

How about posting some diagrams of the system and/or some code you're having problems with,

 

[p11]

1000 words ,each having 20 bits .actually am trying to design a mini version of the entire project first .1.e after 100 ns 1000 words come each having 20 bits ...

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In the first 100ns , a data set is received .
Put it in a buffer as you receive.

For the next 100ns form or point to a separate buffer to receive next set of data in the next 100ns.

When you are receiving 2nd set of data , you can process 1st set in the first buffer and clear it or whatever you want to do.

In the 3rd slot , point to the first buffer if possible or a separate buffer. repeats for ever...

dont know whether it meets your requirement. But this is one possible solution.

sir processing is not an issue for me ... my problem is with transfering , i.e how to transfer this huge data set into a buffer , parallel transfer require so many signals which is not possible to implement . serial needs time .again another problem...

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Why such an old ISE version?
What is your clock speed?
How can your data width "vary later"?
1000 what? bits or words? 20 bits per word?
What are the interfaces you're using?
You still have not answered these questions from earlier - without more details we cannot do anything more than guess.






actually now since interfacing is not possible , so i am designing an LFSR(linear feedback shift register) of 20 bits which is providing random numbers which am considering as input data . Am storing those data in a memory and after every 100 ns , i am transfering this data from this memory to another as if this memory now is acting as a data source .This much i have done. but i am having problem with data transfer , because simple parallel transfer of so many 20 bits data from 1 memory to another is not possible.

i dont have any diagrams now , i will try to update soon . Here the LFSR is running at a clock time period of 2 ns.

 

[TrickyDicky]

clock period of 2ns will not be possible on a spartan 3E, you might be lucky if you can get it faster than 5ns.
From your description, getting the data moved in half the time it would usually take will require you to double the bandwidth somewhere. because you cant double the clock, you'll have to double the data path width.
From your descriptions, it sounds like you really dont have a clear idea of what you're doing.

Why does it need to be transfered in 100 ns?