Pipeline a circuit with loop

[davyzhu]

Hello,

I was told that a large combinational logic can be break by D-FF to meet the timing requirement. I have used it this week by verilog, you may see the style below.

But the simulation seems to be all wrong. I have check all of the signals and found there is several loops in my circuit and affect the data_tmp again.
Is there any reference on how to pipeline a circuit with loop in Verilog or VHDL manually? Thanks.

----.....---(data_tmp)--->[D-FF]--->(data)----|
^--------------------loops------------------------|


//-----------------------------
// Pipeline by verilog
//-----------------------------
assign data_tmp = { large combinational logic };

always@(posedge clk) //modified
if(reset)
data <= 0;
else
data <= data_tmp;

//----------------------------
// End
//----------------------------

Note: Sorry, I forget the posedge on this post. But my source file has the posedge, and the result is wrong.

Regards,

DAVY

 

[arthur]

F-F is sensitive circuit.
Add "EDGE" before "clk" as following
always @(posedge clk)

 

[spauls]

you can trigger your FF with either posedge or negedge of clock

 

[wein]

because your coding style is latch base design ,
you can change to

assign data_tmp = { large combinational logic };

always@(posedge clk)
begin
if(reset)
data <= 0;
else
data <= data_tmp;
end