Pin assignment in SoC

[moon333]

Hello everyone, I study circuit SoC (for example Cyclone V).
I'm a little confused about the pin assignment. Let's take a IC Cyclone V 5CSEBA2(link) for example.
Do I understand correctly that the HPS pin are indicated in the columns HPS Pin Mux Select 0..4, only owned by HPS? Or can they also be attributed to FPGA functions?

I also want to clarify, I understand correctly that the DDR memory controller for HPC and FPGA is common and, as a result, the pin are also common. Is this a correct statement?

Can you please tell me what is the purpose of the column for VREF?

Thanks in advance!

 

[bansalr]

For pin assignment there are certain rules defined by vendors. Only pins defined for user I/O can be assigned. There are more rules bankwise, IO standard etc.

Just see the FPGA vendor document for more information.