Phase Shifting the Clock

[imbichie]

Hi friends,

I wants to phase shift the clock which is used in the process, means the clock is used in the sensitivity list. For example, my clock is 200 Mhz, so i wants to generate a clock with same frequency but different phase (say, 90 or 45 degree). the thing we have to noted is that the same clock is used in the process statement.Also there is no other clock available which is higher than this.

So, is there any way to generate a phase shifted clock without using any PLL or DLL.

Thanks in Advance

Regards
imbichie

 

[FvM]

You won't achieve a stable phase shift without a PLL. Logic gate delays can be used, but must be expected to vary with PVT (process, voltage, temperature) over a range of about 1:2. With respective timing constraints, a synthesis tool will try to achieve specified timing relations of clocks and signals by utilizing routing delays. Alternatively, you can insert logic cells manually and protect them against removal during design optimization.

I don't exactly understand what's the problem with process sensitivity lists. Clearly, a synchronous (edge sensitive) process can have only one clock. Utilizing the same clock (also delayed) as an additional asynchronous input signal won't make sense, normally. But anyway, you have to check, if the intended construct can be inplemented according to the hardware features of the logic family. If the answer is yes, there will be a way to implement it in HDL, possibly by instantiating low level primitives from a vendor library.

If the logic family don't allow the design construct physically, there's no HDL trick to overcome the restriction.

 

[lostinxlation]

if you don't make it a chip and it's just for simulation purpose, just use delay# to delay the signal by whatever amount you want. It's not possible to implement the phase shift reliably without PLL/DLL on silicon, though.

 

[imbichie]

very Thanks to All,