phase frequency detector

[curious_mind]

I have two sine signals(50Hz) A and B. B changes its phase relative to A from 0 to 360 deg. All I need is DC voltage 0 to 10V indicating the phase, which will display in DPM.
I was looking for non software based solution. I looked at phase frequency detector IC, but all of them are for the range in Ghz. Could anybody suggest idea. Measurement accuracy required is 0.02%

 

[KlausST]

Hi,

As written before ... you need to consider the whole chain. Simply chosing a 0.1%VRef is not enough.

And yes, there are 24 bit ADCs. But this is "resolution" .... 16 bit accuracy is a different story.
Additionally .. even most 24 bit ADCs barely achieve 15 or 16 bit ENOB (just noise free precision. Still not 16 bit accuracy)

Klaus

 

[danadakk]

And yes, there are 24 bit ADCs. But this is "resolution" .... 16 bit accuracy is a different story.

Absolutely concur, one of my primary observations and complaints is that full error
budget of the entire signal path is not taught in schools, or so it seems.

Here is a processor with 20 bit that gets close to 20 bit ENOB :

CY8CKIT-050B - Infineon Technologies

www.infineon.com

Another (24 bit on processor) :

The above not complete signal path, but doies include G element

And then of course we use CDS to rid ourselves of noise impacting ENOB.


Regards, Dana.

 

[D.A.(Tony)Stewart]

I have two sine signals(50Hz) A and B. B changes its phase relative to A from 0 to 360 deg. All I need is DC voltage 0 to 10V indicating the phase, which will display in DPM.
I was looking for non software based solution. I looked at phase frequency detector IC, but all of them are for the range in Ghz. Could anybody suggest idea. Measurement accuracy required is 0.02%

Why do you need this?

 

[curious_mind]

One important concern I have is that originally signals are sine waves and they are converted to square through ZCD. If sine waves are noisy then ZCD outputs will go crazy. Therefore I was thinking , if PLL could be used which can eliminate the noise (using loop filter). Using reciprocal counter is great idea, but noisy inputs is sufficient to toggle lot of bits

 

[FvM]

One important concern I have is that originally signals are sine waves and they are converted to square through ZCD. If sine waves are noisy then ZCD outputs will go crazy. Therefore I was thinking , if PLL could be used which can eliminate the noise (using loop filter). Using reciprocal counter is great idea, but noisy inputs is sufficient to toggle lot of bits

Please review my comments in post #4. For the targeted phase accuracy, you surely need to filter the input signals, with or without a PLL. Otherwise harmonic distortion can create severe phase errors in addition to noise induced random variations.

 

[curious_mind]

I found PWM to analog converter, https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2645.pdf. Looks promising. PLL phase comparator generates Pulse width proportional to phase change. Connecting PLL to this IC can directly produce analog output. I wonder how settling times are minimal for 50Hz inputs?

 

[KlausST]

Hi,

PWM to analog:
In simplest way just a low pass filter.

"Settling time" (text) can't be designed nor calculated.

Better use numbers to tell us your requirement.

Klaus

 

[dick_freebird]

Again, there's a big difference between "proportional to" and
"measuring accurately and repeatably". Are you giving up your
0.02% accuracy "requirement"? If not then why bring up simple
approaches using 5-10% tolerance parts and no calibration
plan?

You evidently want to invent something other than the options
proposed thus far. But restarting the conceptualizing over and
over is not much like progress. Even if it is more entertaining
than getting down to the engineering part of it.

 

[danadakk]

@OP

Settling time for a step change in PW can most certainly be calculated. Thru
classic LaPlace and other non linear techniques (to handle phase detector
non linearities) and of course the loop filter behaviour.

Gardner, Dean Banerjee, others, have analysis in his various pubs, many IEEE papers
on analysis of non linear behaviour in PLLs, eg. phase detector focus.

The general T(s) of a loop and its response to a step change in phase
readily evaluated. Crcuicial in some applicatiopns, not the least communications.


Regards, Dana.

 

[curious_mind]

Let me again clarify. I require 0.1 deg accuracy in 360 deg span. In terms of timing it stands as 4us. I understand that PC2 or PC3 phase comparators(74HCT4046A) are capable of generating accurate phase difference between two signals ( I connect signal A to reference pin and B to VCO input pin). IN order to convert phase difference (which reflects in terms of duty cycle) to analog, I propose to use PWM to analog converter as mentioned in #26. I am trying to understand whether it is a tangible solution.

 

[danadakk]

The LTC part has selttling times of (and those shown only as typical) :

Dying to know how they did the measurement and meaurement to 12bit conversion, a flash converter
and 4000+ comparators and encoding array/LUT ? I guess in 1 uS they could do a ramp and a clocked
counter running ~ 100's Mhz.......?

Note the part has a G error approaching 1%, absolute accuracy low.......


Regards, Dana.