PEX with no r/c

[AllenD]

Hi Team
May I please ask a question regarding PEX extraction.

In PEX, if I select
extraction type: transistor level, No R/C, No inductance,
format: calibre view Use names from: schematic

After the extraction, I have verified that in calibre view, the only components are mosfets (each mosfet symbol in calibre view represent is one finger of mosfet in schematic).

My question: is should this post layout simulation EXACTLY same as the schematic？ Or they should just be pretty close but some difference is OK?

Thanks
Allen

 

[Dominik Przyborowski]

Depend to process and thus models.
If process is old and PDK is using modules like bsim3, then simulation show the same results as for schematic netlist.
However, Bsim4 used in some 130nm and beyond includes WPE effects, so you should be able to see variation in VTh of devices (and consequently in current, etc). Modern processes (28nm and beyond) has modeled LOD as well, so differences might be higher.

 

[timof]

LVS and extraction identify all the layout / geometry parameters for MOSFETs and for other devices, such as AS, AD, PS, PD, and many other parameters (LOD, WPE, ...).

Device matching may be affected, and device electrical characteristics.

How far this will be from the schematic - depends on the technology, foundry, PDK, etc.
If these parameters would not impact the electrical characteristics, they would not be introduced into SPICE models.