Performing gate level simulation

[ikki]

vsim-sdf-3240

hi there, i wanna do a gate level simulation on my design after synthesis using lenardo spectrum.

I generated .vhd and .sdf file from leonardo spectrum. Can some one guide me on how to do the simulation using modelsim se ? I tried to compile it but it seems that im missing some library as the modelsim doenst understand the instantation of the gate used in the netlist from leonardo spectrum....

Also, issit better to do gate level simulation in verilog format netlist instaed of VHDL format netlist ? ...

# vsim -sdftyp /tb_adder/UUT=C:/test_synthesis/adder/synthesis/half_adder.sdf work.tb_adder
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../std.standard
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../ieee.std_logic_1164(body)
# Loading C:\FPGAdv71LSPS\Modeltech\win32/../ieee.numeric_std(body)
# Loading work.tb_adder(behavior)
# Loading work.half_adder(behavioral)
# ** Warning: (vsim-3473) Component instance "ix1 : and02" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix7 : aoi21" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix104 : inv01" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Warning: (vsim-3473) Component instance "ix106 : inv01" is not bound.
# Time: 0 ns Iteration: 0 Region: /tb_adder/uut File: C:/adder simulation/half_adder_0.vhd
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(14): Failed to find INSTANCE '/tb_adder/uut/ix1'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(23): Failed to find INSTANCE '/tb_adder/uut/ix7'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(34): Failed to find INSTANCE '/tb_adder/uut/ix104'.
# ** Error: (vsim-SDF-3250) C:/test_synthesis/adder/synthesis/half_adder.sdf(41): Failed to find INSTANCE '/tb_adder/uut/ix106'.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "C:/test_synthesis/adder/synthesis/half_adder.sdf".
# Time: 0 ns Iteration: 0 Region: /tb_adder File: C:/adder simulation/tb_adder.vhd
# Error loading design

these are the error encountered ..

Added after 1 hours 14 minutes:

Ok i managed to solve the component problem but now when i wanted to simulate the netlist with sdf for back annotation, it ggives error from the sdf file ...

# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(20): Instance '/tb_adder/uut/ix1' does not have a generic named 'tpd_a0_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(21): Instance '/tb_adder/uut/ix1' does not have a generic named 'tpd_a1_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(30): Instance '/tb_adder/uut/ix7' does not have a generic named 'tpd_a0_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(31): Instance '/tb_adder/uut/ix7' does not have a generic named 'tpd_a1_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(32): Instance '/tb_adder/uut/ix7' does not have a generic named 'tpd_b0_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(39): Instance '/tb_adder/uut/ix104' does not have a generic named 'tpd_a_y'.
# ** Error: (vsim-SDF-3240) C:/test_synthesis/adder/synthesis/half_adder_0.sdf(46): Instance '/tb_adder/uut/ix106' does not have a generic named 'tpd_a_y'.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "C:/test_synthesis/adder/synthesis/half_adder_0.sdf".
# Time: 0 ns Iteration: 0 Region: /tb_adder File: C:/adder simulation/tb_adder.vhd
# Error loading design

I believe there are mismatch between my netlist and sdf ... wonder why this happen ... I generate the sdf from the same synthesizer and right after the netlist...
I wonder is it because of my region was set wrongly ?

I set my region to be tb_adder/uut that represents mytestbenchname/instancename of the design

 

[ljxpjpjljx]

i think you can search the missing module in the file first!

 

[ikki]

there is no missing module i believe.

I only have tb_adder.vhd , half_adder.vhd (netlist) and half_adder.sdf I cant find the generic signal that it popped as error.

 

[rsrinivas]

make sure u r compiling ur library files

 

[NITIN BHARDWAJ]

Hi,
How you resolved the component issue. Do we need to compile .lib or libraries in simulator before we can get throgh the Netlist simulation.

Regards;
Nitin