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What about FFT test?
Is it a good way to convert digital output code to analog using DAC to test,
Can I take a FFT test for my ADC digital output code without using DAC?
FFT is possible with and without DAC.
A DAC is flexible. But a DAC has it's own errors. Be sure not to measure the DAC's errors, but only the ADC's errors.
Hi dear Klaus,
Thank you,
I'm confused about where to consider as the nodes to take the FFT analysis without DAC!
That's why I've tried to use a DAC to make digital output to a known Vout to be able to take FFT, it was a wrong way
Applying input source like what you said and taking FFT from where..
Did you read tech notes about how to test an ADC?
I doubt it ... At least you don't tell us about your setup...
So we have to guess a lot...But guessing takes a lot of time and effort...and maybe only a small part of our guessing is correct for you..
****
Let's concentrate on one parameter. SNR.
SNR means Signal to Noise Ratio.
So obviously you need a signal. A signal is defined in waveform, frequency and amplitude. I recommend to use pure sine.
But frequency and amplitude I can not recommend. This is your job. But values must fit to your ADC.
You did tell nothing about sampling frequency (range) and input voltage range of your ADC. So we can not know.
Also you need a source for this signal. We don't know where the signal comes from. It 's your job to decide this.
Your signal quality regarding noise obviously should be far better than your ADC.
We don't know about you ADC physical interface and protocol.
We don't know about your memory, nor your FFT depth...
I recommend to synchronize your signal source and your ADC sampling rate in a way that you can avoid windowing digital data (hanning, hamming..).
I recommend to calculate the fundamental signal amplitude from the FFT values.
Then calculate the RMS noise from the FFT values (without DC, fundamental frequency and without overtones).
Then calculate SNR.
I expect all this is not new for you, because you already should have read about how to test an ADC before you started this thread.
It still is unclear if you need our help to tell you:
* the basics of ADC testing
* what hardware to use
* how the calculations have to be done.
* ...
Hi, dear
I'll involve these points and I'm appreciated.
Of course, input voltage range, sampling frequency and... are defined by me and design of the parts were base on such parameters.
The situation is about someone that's finishing something for first time, the project is my M.S thesis and my problem was that all of parameters were on my own custom, and my supervisor is not superviser by mean, the project was undifined totally, it was ridiculous like walking in the center of a desert with no compass. Trust me it was a miracle to finish it all alone. I'll share the results finally.
Thanks for your guidance.
First eliminate all static sources of error using a calibrated DAC. THis includes ground shift of Vref from digital currents and thermal drift of Vref.
When I designed a 12bit SCADA system in the 70's I used BB 12 bit ADC's and DAC and was happy with DAC but had issues with monotonicity missing codes and hysteresis which I presumed was an early flaw in the Vref grounding internally with SAR comparator ground currents. THis was at the time a state of the art SAR ADC hybrid in ceramic inside a shielded can.
To test the DAC I used a scope ac coupled and detected each step using a suitable clocked counter to drive the parallel input DAC. The response error and linearity was +/- 1/2 LSB as expected with very little error noted by scope step size drifting to zero (AC coupled) Then changing speeds and variable load could verify the output impedance of the driver and load regulation errors. No problem.
TO test the ADC I used my confirmed calibrated DAC and now use the ADC output to drive the DAC and compare In - Out using Scope A+ B invert. When I swept with DC I could see the errors clearly at boundaries of ...xxx111xx to ...xxx100xxx and visa versa with a hysteresis effect. Thus confirming a Vref issue in the DAC or a droop problem in the S&H. Note the hold capacitor must either be COG/NPO or Film as anything else will have a memory effect and sag or droop with load impedance must be negated. RC time droop during SAR calculation in ns in your case or us. Mine was 20MHz sample rate. in my case I used film cap and CMOS S&H had no crosstalk or droop in the held value up to the bandwidth of interest and all bandstop filters had zero group delay in the passband. YOu need to consider how to do this with eye pattern data rate tests or use group delay measurements. THe S&H error is a big challenge for error with crosstalk and transients that are polarity and level dependent. SHielding, ground guard tracks , "active guarding methods " and Common mode filter rejection with ferrite are often necessary to ensure signal integrity before ADC.
Thus you can determine many sources of error simply using a scope and input AC waveforms from DC, sine, mixed sine, square pulse and sinx/x to measure each source of error and compare with with error budget. The SNR will be a result of all the DC and AC noise sources including sensor EMI crosstalk, PSU noise and quality of signal source. Using a PRSG data pattern limited by the bandwidth of your input filter clocked at suitable rate is also another way to measure eyepattern distortion or group delay distortion in your filters and also your ADC quantization errors.
I know this is old school, back in the late 70's but it worked for me. So many people ignore Vref errors and ground shift noise and hysteresis effects at certain bit boundaries and lump the results into one reading. It is more important to have test methods for isolating each source of error, like for linearity and asymmetry and harmonic distortion.. Use a square wave with symmetrical rise fall times and measure the 2nd harmonic as -60 to -80 dB for quality of source then inject into the ADC and see the results of asymmetry at different source frequencies and DC offsets.
I wasn't in the desert but in a small R&D lab on my own.. but I can understand your challenges.
I had no help and was only out of UofM for a couple years. In the end the system worked well.. (automated Eddy CUrrent inspection probing with robotics for Candu Nuclear Secondary heat exchangers with 2000x 60m U-tubes per tube sheet heat exhcanger and dozens per reactor building with many reactor buildings and an ADC resolution of 0.1mm of pipe ( desimated to 0.2mm resolution at 10MHz sampling rate with controlled probe drive speed rates and calibration holes and slots for the quadrature 100/200kHZ eddy current probe signals. to measure down to 100 ppm change in vector impedance with high SNR.) THis allowed them to detect metallurgic flaws before a heavy water leak could occur at 10k atmospheres of pressurized heavy water.
When I designed a 12bit SCADA system in the 70's I used BB 12 bit ADC's and DAC and was happy with DAC but had issues with monotonicity missing codes and hysteresis which I presumed was an early flaw in the Vref grounding internally with SAR comparator ground currents.
Oh yes. I´ve build an AD8320 16 bit ADC application. I tested the performance and recognized missing codes around 0x4000, 0x8000 and 0xC000. A bigger capacitor (1uF instead of 100nF) at VRef was the solution. Then the overall performance was far better than the datasheet said.
--> monotonicity, no missing codes, DNL often will be influenced by external VRef circuitry...
In my case Vref and entire ADC was internal to BB hybrid (883B parts n.g. yet Ind. parts all ok!) Obsolete now. and Analog G , Digital Gnd currents were laid out OK.
Thanks @SunnySkyguy,
It was impressive, and it is, when such a long joyful journey even when nothing is not obtained, after one sunrise will reach to the true results. I'll work on, finally sharing what I've done.
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