PCIe Design Problem (BAR and Addressing)

[jasonkee111]

Hi

I have a design which consists of 1 PCIe. PCIe communicates with the other component like onchip memory (slave) via BAR.

PCIe Design
http://i48.tinypic.com/n71krl.jpg
As you can see, PCIe BAR 0 connects to CRA(control register of PCIe) and Onchip Memory.


I have tried my design on the my PC which has PCIe slot and it is working properly. However, the same design fails in targeted platform. The targeted platform has a module called nanoETXexpress SP and uses Win CE 7. It uses Intel System Controller Hub. According to the Intel System Controller Hub, page 61, table 10, PCIe can be configured in anywhere in 32-bit range.

nanoETXexpress SP (1GB DDR2 RAM and 512MB flash)
**broken link removed**

Intel System Controller Hub
download.intel.com/design/chipsets/embedded/datashts/319537.pdf


The table shows the summary of the result :
http://i50.tinypic.com/30kyl90.png


I am suspecting the targeted platform address mapping is overlapping with my design (PCIe BAR base address). Any advice would be appreciated.

Do let me know if the the image can't be seen.

Thanks

---------- Post added at 10:24 ---------- Previous post was at 09:10 ----------

Mistake in onchip Memory size. It is 409600 bytes instead of 4096 bytes.