Pattern recognition in Verilog (word problem)

[kukurigu]

A finite state machine has one input and one output. The output becomes 1 and remains 1 thereafter when at least eight 0's have occurred as inputs. No RESET input - big problem!!!

How to design this in verilog? ... or idea for schematic
Can you help?

 

[bogdanm]

Maybe I don't fully understand your post, but I think that adding a reset input to your state machine that sets the state to the initial state can solve the problem. It doesn't even have to be synchronous.

 

[kukurigu]

The problem is to solve this task without RESET input!!!

 

[bogdanm]

Why would you design a state machine (that contains sequentially logic) WITHOUT a reset input? Maybe you should reconsider your design.

 

[wllee]

Every design can add reset to solve the initial condition. If your design
don't reset pin input, maybe you can add power_up reset circuit in your design.

 

[bogdanm]

I would say that every design that uses sequential elements MUST add a reset signal, at least to set up the initial state ... You can't just power up a sequential circuit and hope that all of its elements are initialized in the way you wish. Instead of trying to find a way to reset a state machine without a reset signal I would concentrate on how I could add a reset signal to the circuit.

 

[kukurigu]

I agree with you, but the question is: is it possible without POR circuit and reset input.

 

[bogdanm]

You could probably jump back from the final state to the initial state after the pattern recognition algorithm detected a pattern. This will work without reset, however I don't know know how you'll put your machine into the initial state without reset ...

 

[shell3]

Actually the verilog version will work as shown below, because "shift"
will start with all 'x', after eight zeros are shifted in the out will go HI
and stay HI forever.
The gate version will not work because the "shift" may contain any
value from 0 to 255. The result will be correct only when the least signifiant bit is HI.

module fsm (in, out );
input in;
output out;
reg out;
reg[7:0] shift;
always @ ( negedge in ) begin
shift[7:0] = {shift[6:0], 1'b0};
end
always @ (shift) begin
if (shift== 0)
out = 1;
else out = 0 ;
end
endmodule

Regards,
Shell3