dragonwarrior1
Newbie level 1
Hi,
Theres a state machine that makes output 1 if it finds the sequence "11001100" in the input, else makes output 0. If it finds the sequence "111001100" or "110011000" it does not find a match and will make output 0. How do I implement this in Verilog ?
Thanks in advance !
Theres a state machine that makes output 1 if it finds the sequence "11001100" in the input, else makes output 0. If it finds the sequence "111001100" or "110011000" it does not find a match and will make output 0. How do I implement this in Verilog ?
Thanks in advance !