Pattern matching using state machine

[dragonwarrior1]

Hi,

Theres a state machine that makes output 1 if it finds the sequence "11001100" in the input, else makes output 0. If it finds the sequence "111001100" or "110011000" it does not find a match and will make output 0. How do I implement this in Verilog ?

Thanks in advance !

 

[beowulf]

input in
reg [8:0] seq;
reg pass;

always @ (posedge clk or negedge rstn)
if (~rstn)
seq <= 'b0;
else
begin
seq <= {seq[7:0],in};
if (seq[7:0] == 11001100)
pass <= 1'b1;
end

// Add logic to deassert pass

Please post a better solution or point out if there are any corrections to this

 

[nisshith]

first mistake is that if it is a sequence detector input must b of one bit only with one bit coming in on in every clock cycle.
u have to make a state machine first. i think it will have 12 stages hence 4 flip flops must be used to control state vectors. Make a state machine and do the verilog coding for the same.

 

[beowulf]

The input here is a single bit 'in'
It is bit shifted into a register...any particular reason why a SM is required...

 

[nisshith]

it will work fine in verilog but i think it will take more hardware, not a feasible design.

 

[beowulf]

This design takes 9 flops+1 for pass and few gates, will a SM based design take less logic..?
It will need the same no of flops...

Will it be more readable..?