shaiko
Advanced Member level 5
Hello,
While debugging an old design I came across the following code:
Question:
Why does this code even compile ? To me it seems that the line marked in red cause 'x' to be driven by 2 drivers...
What am I missing here ?
While debugging an old design I came across the following code:
Code:
alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.
begin
process ( clock ) is
begin
if rising_edge ( clock ) then
if x = '1' then
some_other_signal <= a + b ;
[COLOR="#FF0000"]x <= '0'[/COLOR] ;
end if ;
end if ;
end process ;
Why does this code even compile ? To me it seems that the line marked in red cause 'x' to be driven by 2 drivers...
What am I missing here ?