parametrized adder tree in Verilog

[Hallolo]

Hi all

Iam trying to design a paranetrized adder tree, i tried doing so using multiple generate loops, but what i noticed was that in the second generate loop and third the previous working first level part of the adder tree stops working.
Any suggestion on how to implement an adder tree that can take any number of inputs ( as a parameter) .

Regards