PA design with the BLF544 MOS

[pepewaw]

I'm designing the last stage of a PA which is to operate at 700MHz (around 50Mhz bandwidth) at 10W. Due to availability, It´s convinient to use the BLF544, which according to the datasheet can be made into a 960Mhz 20W PA.

However, looking at the S parameters downloaded from NXP (which are listed below)

@700MHz

S11 = 0.895 177°
S21 = 0.392 7.5°
S12 = 0.0603 -60°
S22 = 0.875 -170°

I find S21 being too small to get any significant gain, yet, according to the MSG formula, it says that theorically I could theorically obtain around 9dB gain.

My questions are:

+ how much of this theorical value can I expect to achieve in practice?
+ I´ve tried matching the input and output for maximun power transfer (complex conjugate impedances); is this the correct way to achieve maximun gain?
+ Every time i match the output, it mismatches the input, and Vice versa. Is there a recomended procedure/steps to follow to avoid this?

Thanks for any tips

PS: Just in case it's necessary, the input and output impedances are 50Ohms.

 

[FvM]

The said S-parameters are small signal. Apparently, they are more or meaningless for PA operation. You should
rather refer to the power gain specifications in the datasheet and the empirical impedance matching circuit. I won't expect
much benefit from calculating impedance matching based on the given S-parameters.

At best, S11 and S12 have some relevance with large signal, but the output matching should be better determined by load pulling.

 

[vfone]

These are low signal S parameters at 40mA bias provided by NXP.
For maximum output power and best efficiency have to match the transistor for optimum input and load impedances.
For example NXP recommends for 960MHz:
Optimum input impedance: 1.2 + j4.8 Ω
Optimum load impedance: 2.6 - j3.1 Ω