Output real port initial value

[Khaled Ibrahim]

I'm simulating a mixed-signal design including spice/vhdl models using ADVance MS and as far as I know, the initialization of real signals will be the value given if any, otherwise it'll take the first value of the real range which is (-1.0e38).

What I'm facing is that I'm putting a check (assert statement) for an input port connected to that output real port so that it'll generate an error message if the value was (-1.0e38) and regardless what I'm putting as an initial value, the simulator generates this error!!

Any explanation?

 

[Harmasha]

Hi,
Did you check the connectivity of teh port. Because when I used verilog I used to get default real value always read by the port. Check first whether your input port is reading the initialized value. Hope this works. Any way when you are done do post your findings.

 

[Khaled Ibrahim]

And how could I know that the input port is taking the initial value? When I use the Structure and Objects wnidows to see what is the initial value of all the singals, I find that it is well initialized from inside each model but not from the top level!! I mean the initial state of the signal is different in inside the model from outside it (the top level circuit)!

 

[Harmasha]

Hi,
Then the problem should be with the scope of your object.
Try having them in Top and access them using direct access or dot method and cross check them.
The same thing happened to my module when i had it ini Verilog. So this should fix it.