orcad capture cis - convergence problem..

[devidayalsoman]

I'm trying to simulate a first order delta sigma modulator and the netlist is given below. i have come across convergence problem. can anybody help me?






** Creating circuit file "firstorderdsmsim1.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\OrCAD_16.0\tools\PSpice\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 1s 20ns
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"



**** INCLUDING SCHEMATIC1.net ****
* source FIRSTORDERDSM_VER1
.EXTERNAL OUTPUT Vref
.EXTERNAL OUTPUT Vref+
.EXTERNAL OUTPUT Vref-
.EXTERNAL OUTPUT cmd/
.EXTERNAL OUTPUT +5VL
.EXTERNAL OUTPUT cmd
.EXTERNAL OUTPUT Vcc
.EXTERNAL OUTPUT Vdd
X_U4A $D_HI N04986 N13798 $D_HI CMD CMD/ $G_DPWR $G_DGND 74HC74 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R1 N04986 +5VL 1k
U_DSTM1 STIM(1,1) $G_DPWR $G_DGND N13798 IO_STM IO_LEVEL=0
+ 0 0
+ +0 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT
V_V2 VREF+ 0 1Vdc
x_U1A VREF- VREF CMD VCC VDD CD4016A
V_V3 +5VL 0 5Vdc
C_C1 N05719 N03364 1n
R_R2 N07859 N05719 10k
V_V4 0 VDD 12Vdc
V_V5 0 VREF- 1Vdc
x_U1C VREF+ VREF CMD/ VCC VDD CD4016A
X_U2 N07707 N05719 VDD VCC N03364 0 LM311
R_R3 0 N07707 2.2k
X_U3 0 N03364 VCC VDD N04986 0 LM311
V_V6 N07859 0
+SIN 0V 5V 1kHz 0 0 0
R_R4 VREF N05719 10k
V_V1 VCC 0 12Vdc

**** RESUMING firstorderdsmsim1.cir ****
.END

 

[atripathi]

can you please share your schematic?

 

[kodar]

Check the command .TRAN 0 1s 20ns in your spice netlist. It seems not correct. Your are set a maximum step size of 0s which have no sense.