Operation of D type flip flop? (set! and reset!)

[cupoftea]

Hi,

From page 4 of the 74HC74 dual D type flip flop
https://www.mouser.co.uk/datasheet/2/916/74HC_HCT74-1319854.pdf

…if we put set! and reset! both to high, then they are just effectively ignored?
Also, if we put reset! to low, (and set! Is high) then Q goes low, and doesn’t have to wait for the clock before going low?
Also, if we put set! to low, (and reset! Is high) then Q goes high, and doesn’t have to wait for the clock before going high?
Also, if we put set! And reset! both to low together, then Q and Q! both go high, and don’t need to wait for the clock to do that?

 

[dick_freebird]

You ought to find this in the truth tables, but may also see
notes about "set overrides reset", or vice versa, or to the final
question notes that the outputs depart from a complementary
state when an abnormal coincidence is applied.

The last-released of {Sb, Rb} is the winner. What happens in
cases of conflict may depend on the internals (like, all-NAND
vs tri-state-inverter (w/ some turned into NANDs) may change
whether Q and Qb both go low / high, or remain complementary;
have seen standard cell libraries where Qb is only an inverter
stage from Q or Qi).

But all that ought to be in the truth table.

 

[KlausST]

Hi,

RD is active when LOW, asyncronous means not waiting for clock edge.
SD is active when LOW, asyncronous means not waiting for clock edge.

--> Thus both are inactive when HIGH, nothing happens
* If RD = LOW and SD = HIGH then --> RESET is active thus the output Q immediately becomes LOW, Qn = HIGH
* If SD = LOW and RD = HIGH then --> SET is active thus the output Q immediately becomes HIGH, Qn = LOW
* If RD = LOW and SD = LOW then --> the output Q immediately becomes HIGH, Qn also HIGH.

The last state is rather uncommon - at least for me.

Klaus

 

[danadakk]

Also, if we put set! And reset! both to low together, then Q and Q! both go high, and don’t need to wait for the clock to do that?

Thats correct, you can see that from the following -

However I saw another truth table where the implementation was different, and
simul set and clr, and clock input, the output was a f() of all 3.

Yet on a third datasheet a simul set and clr cleared the output.....

And still another where set and clr could be synch or asynch.....

Chk the datasheet as always.


Regards, Dana.

 

[FvM]

All questions related to clock can be simply answered by considering that !S and !R are asynchronous.