Opamp layout doesn't work with parasitic R included

[jalalif]

opamp layout

Hi everybody,
I got a problem recently that I don't know how to solve it. I really appreciate your helps and comments on that:
problem is: I have layouted a two stage Opamp with switched cap CMFB. The Opamp works fine in schematic,the extracted file including parasitic C also works very well but if I include parasitic R, it doesn't work and the peoblem is that although CMFB circuit does his job well and the common voltage of output is the correct value(at mid-rail),but Vout+ and Vout- have some diffential errors. I guess that should be due to the fact that the layout is not %100 symetric and paths to Vout+ and Vout- may have diffenet resistances, I tried my best to make the layout symetric and draw the paths of Vout+ and Vout- the same length but problem still remains. The differential diffence between Vo1+ and Vo1-(outputs of firts stage of Opamp) are around 20mv but the error gets much bigger when we look at the Vout+ and Vout-(outputs of the second stage of the Opamp)due to the gain of the second stage.

Thanks a lof for your help

 

[electronrancher]

op amp layout

which parasitic R is the problem? are you sure you're not running the cmfb circuit at the edge of saturation?

path length should be a problem you look for when searching down offsets less than 1mV - i think 20mV offset indicates a bigger problem..

 

[jalalif]

opamp doesnot work with dc voltage

which parasitic R is the problem? are you sure you're not running the cmfb circuit at the edge of saturation?

path length should be a problem you look for when searching down offsets less than 1mV - i think 20mV offset indicates a bigger problem..

Hi electrorancher,
thanks a lot for your reply. But I wasn't sure what you mean by using cmfb at the edge of saturation.I have used a switched cap CMFB circuit.It worked fine in schematic,I have also measured the open loop PM and ac responce of the cmfb loop and it was good.When I extracted the opamp including the parasitics and did the transient analysis for vin(ac)=0, the ouputs which supposed to be equal and at the midrail,were not equal.Let's say midrail is 900mv,vout+ was 910 and vout- reached to 890 so their common voltage is 900mv which is correct(seems that cmfb has done his job) but their DC values are different. I was thinking that it might be because the layout is not completely symetric and I tried to do the layout as symetric as possible but the problem still remains.The real problem is that the opamp is a two stage ota and even small variations in the dc bias of the first stage has a big effect on the ouput of the second stage.

 

[bastos4321]

2 stage op amp layout

One way to minimize that effects in fully differential amplifiers is to draw only half layout of the amplifier, then join the two equal parts to form the complete amplifier. In this way the resistances for each side of the amplifier are equal.

bastos

 

[amitbhaiji]

what if layout doesn;t work

Its seems like that your problem si due to the input reffered offset. which is saturating yo ur output stage and this offset will be there even (may be reduced but since gain of your stage is high ) if you make your layout ideal.
try running the AC analysis (rather be PAC anlysis as you are using the switch cap based CMFB) with the topology which work as the unity gain at low frequency and openloop at high frequency...

I presume that your are going to use your diffrential amplifier in some feedback configration..

Amit

 

[felixkao]

layout op amp

Did you check the extracted R is accurate??
I found out a problem recently that is the extracted R is too large in mos.
Maybe you can check that.

 

[mady79]

It is for sure that it is a input referred offset caused by mismatches .

Do the following experiment to the design,given a common mode at the input and check for Vo1-Vo2(First stage output) and check for Vout1-Vout2 Second stage output .

Second experiment would be to consider 10% variations in VDD and measure the offset .If any transistor are in edge of saturation ,then you can fine tweaking can be done .

IF the design is ok ,then there is a serious problem in layout .Use common centroid for the input pair and second stage is more critical ,if there is a slight mismatch in PMOS and NMOS in second stage ,then this will lead to an offset .

Careful routing ,and proper matching will work .
Hope this would .
:!:

 

[stefano2m]

I'm not sure if my opinion is correct, but my ideea is this: try to increase the length of the MOS transistors as active load from the differential pair in order to have a better matching of the DC currents. Maybe you don't have such a good mathing in currents and when you included R parasitics, this difference became important.

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stefano2m