Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

OPamp Design with National Semiconductor tecnology 180 n

Status
Not open for further replies.
V

vdavi81

Newbie level 4
Joined
Nov 26, 2009
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Italy
Activity points
1,331
Hello . I'm italian student . I'm trying to design an opamp in cadence. I'm working in my university with National Semicondictor tecnology at 180 nanometer..... What Can I set all transistor size.
Now I'm using a circuit for 2 state...the first one is a differential couple of Pmos whit Nmos load. The second is a simple common source amplifier. The BIAS is a simple Current mirror ......

1)I have to define a SR, CMR+,CMR-, offset ecc.. Where can I find the appropriate documentation?
2)Someone has a circuit that running from me? ...or where can I find a good circuit working?

Thanks.
Helllo Davide.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top