NPN in feedback loop

[cupoftea]

Hi,
Imagine You have a variable gain NPN in the Flyback feedback loop...like as in page 7 of this...

DER-243

https://www.power.com/sites/default/files/documents/der243.pdf

...You obviously dont want it there...but must have it, to keep opto current down.
So which NPN has the least variation in gain?

The Flyback has VAC in = 90-125VAC, and will be in continuous mode for most of that, though not very deeply so.
Also, its a TOPswitch-HX, so its voltage mode.
Fsw = 65kHz, Lp=1.07mH Np/Ns = 84/19

There is no fan in the unit...its just convection cooling as best as poss in the enclosure.

MMBT3904

https://www.onsemi.com/pdf/datasheet/mbt3904dw1t1-d.pdf

 

[BigBoss]

Since the current which is supplied from this regulator circuit low-presumed- the dependence on Beta of the transistor on regulator performance is negligible. I believe the supplied current is in uA or few mA range
Moreover, the zener diode's (VR1) temperature coefficient is more important than this.

 

[dick_freebird]

To me it looks like the 2N3904 is part of the optoisolation
"photo-Darlington" and the TL431 / LMV321 has the regulation
responsibility. The only problem would be if opto RX leakage
or TX output floor take you away from where a well formed
"1" / "0" from the opto link, is had. But what the "C" node
inside the PI part gets up to, is a mystery to me while the
opto output sure looks "sandbagged" with C.The opto chain
looks like a 1-way pump, not a real time actor.

For all their talk of "integration" that design sure looks "not very".

 

[cupoftea]

Since the current which is supplied from this regulator circuit low-presumed- the dependence on Beta of the transistor on regulator performance is negligible

Thanks, do you imply that beta becomes more tightly toleranced at low Ic?
I think beta is so poorly toleranced, that they dont even bother giving the tolerance band?...youre just expected to know its wide tolerance and make do.

 

[BigBoss]

Thanks, do you imply that beta becomes more tightly toleranced at low Ic?
I think beta is so poorly toleranced, that they dont even bother giving the tolerance band?...youre just expected to know its wide tolerance and make do.

Q1 and VR1 serve together namely a second regulator/supply for IC when the mains input voltage drops down from a certain point. Because IC is fed essentially from mains volatge but IF this tension is not well enough, this regulator continue to supply the IC. Therefore there is diode between two supplies.
Since the Beta DC should be high enough, there will be no problem at all. Because the Zener current is almost constant and since the transistor is ON state , it will supply required current ( uA or few mA range ) .

 

[mtwieg]

Q1 and VR1 serve together namely a second regulator/supply for IC when the mains input voltage drops down from a certain point. Because IC is fed essentially from mains volatge but IF this tension is not well enough, this regulator continue to supply the IC. Therefore there is diode between two supplies.
Since the Beta DC should be high enough, there will be no problem at all. Because the Zener current is almost constant and since the transistor is ON state , it will supply required current ( uA or few mA range ) .

I think the OP was asking about the role of Q2 in the feedback loop, not Q1.

 

[BigBoss]

I think the OP was asking about the role of Q2 in the feedback loop, not Q1.

I think you're right, my fault.
The darlington pair ( Opto+NPN) both take the decision on voltage regulation so Forward Beta ( because they work in pulsed mode) play a important role. I didn't check the whole circuit but the designer had taken this variations into account and designed for worst case scenarios.

 

[cupoftea]

Thanks, but as you know, the regulation "opto and NPN" pair do not work in pulse mode.

 

[mtwieg]

I didn't check the whole circuit but the designer had taken this variations into account and designed for worst case scenarios.

We'd certainly hope so. Variation in the opto is often fairly large, and the bjt adds onto that. At first I assumed R25 has the role of degenerating the gm of Q2, and also reduces its effect on the overall circuit. But I don't think that applies when the base is fed by a high impedance source (like an optocoupler).

--- Updated Aug 9, 2023 ---

the regulation "opto and NPN" pair do not work in pulse mode.

"pulse mode" meaning what?

 

[cupoftea]

'pulse mode' as in on/off type control

--- Updated Aug 9, 2023 ---

Mtwieg , you were right, the low ohm resistor is for emitter degen.....it also says so in the app note of the top post.
The opto "high z drive" is right too....and ayk, the emitter degen res is still needed.

--- Updated Aug 9, 2023 ---

...as you know, that cct would be horrendous without emitter degeneration....its still pretty horrendous even with it.

 

[Easy peasy]

Is it just me or is there an error on page 7:

namely the transistor Q1 should be NPN and the E - C swapped ?

--- Updated Aug 9, 2023 ---

there is no pulse mode as the opto darlington is fed from a large cap - i.e. stable - ish DC

 

[cupoftea]

thanks, ref error...need to check the TOPswitch datasheet for what is V pin.
The ZM5244B is a 14v zener

BZM5244B PDF

Part #: BZM5244B. Description: SURFACE MOUNT ZENER DIODES. File Size: 78.39 Kbytes. Manufacturer: Pan Jit International Inc..

pdf1.alldatasheet.com

I thought when the bias rail is going above 14.7v, then the pnp conducts into the V pin and shutdown occurs...but will check the TOPsw datasheet...in fact, what i said is unlikely as 14.7v isnt sounding high enough for overvoltage indication from bias coil.....buy ayk it depends on turns ratios.
..usually they have a zener from the bias coil to the chip, which conducts when vout goes OV...and shuts it down.

A look in the top post doc says it shoudl be pnp as it serves the TOP openloop trip...but yes...14v7 sounds low for the zener into q1 base......since due to all the leakage current overcharging of the bias coil.

 

[Easy peasy]

the reason it is likely wrong - is that it is supposed to provide a reg supply of current even during dips into the V pin - as it stands it won't do that very well, also there is only the 100 ohm R limiting base current if the supply goes up - so - really needs swapping for npn and laterally inverting - then it will work as a reg

 

[mtwieg]

'pulse mode' as in on/off type control

I don't see what that has to do with the "opto and NPN"

Mtwieg , you were right, the low ohm resistor is for emitter degen.....it also says so in the app note of the top post.
The opto "high z drive" is right too....and ayk, the emitter degen res is still needed.

...as you know, that cct would be horrendous without emitter degeneration....its still pretty horrendous even with it.

I don't think R25 will actually have the intended affect though, as the base is current-fed, not voltage fed. R25 does not affect the base current of Q2. It also doesn't affect the emitter current. In order to degenerate the gain of Q2, R25 would have to be connected from base to emitter of Q2.

--- Updated Aug 10, 2023 ---

the reason it is likely wrong - is that it is supposed to provide a reg supply of current even during dips into the V pin - as it stands it won't do that very well, also there is only the 100 ohm R limiting base current if the supply goes up - so - really needs swapping for npn and laterally inverting - then it will work as a reg

I was also staring at Q1 for a while... I don't think it's a typo as the schematic clearly indicates a part number for a PNP. I think it would still work as-is, but probably would behave better with an npn as you described. I also feel like it's missing a diode somewhere to protect against reverse bias...

 

[prairiedog]

Is it just me or is there an error on page 7:

View attachment 184315

namely the transistor Q1 should be NPN and the E - C swapped ?

--- Updated Aug 9, 2023 ---

there is no pulse mode as the opto darlington is fed from a large cap - i.e. stable - ish DC

PNP yes- it's an open-feedback loop, over-voltage shutdown. The TOP2xx "V" pin has multiple functions.
If the feedback loop went wonky, the aux winding's high output voltage say >14.6V here would turn on the PNP and inject current to the "V" pin which forces the IC to go into latching shutdown. It's a way to protect the load with OVP.
Typically that circuit Q1 is a voltage regulator giving power to an SMPS IC but Power Integrations steals that on the "C" control pin instead, as part of their patents and IP.