amronasr
Newbie level 3
hi all,
i am using an IP core , I am using the on chip DCM.My problem is when I am simulating using modelsim,the signal is not getting locked. Although that i am getting the output signal .It is Spartan 3A FPGA . I would really appreciate if someone help me.
---------------------------------------------------------------------------
Here is the VHDL code
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock5048 is port
( clock50in : in std_logic;
rst : in std_logic;
clock48out: out std_logic;
locked : out std_logic);
end clock5048;
architecture Behavioral of clock5048 is
COMPONENT dcm5048
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
begin
Inst_dcm5048: dcm5048 PORT MAP(
CLKIN_IN => clock50in,
RST_IN => rst,
CLKFX_OUT => clock48out ,
LOCKED_OUT => locked
);
end Behavioral;
--------------------------------------------------------------------------
and here is the test bench
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_5048 IS
port (clock48out: out std_logic);
END test_5048;
ARCHITECTURE behavior OF test_5048 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock5048
PORT(
clock50in : IN std_logic;
rst : IN std_logic;
clock48out : OUT std_logic;
locked : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock50in : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
-- signal clock48out : std_logic;
signal locked : std_logic;
-- Clock period definitions
constant clock50in_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock5048 PORT MAP (
clock50in => clock50in,
rst => rst,
clock48out => clock48out,
locked => locked
);
-- Clock process definitions
clock50in_process rocess
begin
clock50in <= '0';
wait for clock50in_period/2;
clock50in <= '1';
wait for clock50in_period/2;
end process;
process
begin
rst<='1'; wait for 200 ns;
rst <='0'; wait;
end process;
END;
------------------------------------------------------------------------
Simulation images have been attached
i am using an IP core , I am using the on chip DCM.My problem is when I am simulating using modelsim,the signal is not getting locked. Although that i am getting the output signal .It is Spartan 3A FPGA . I would really appreciate if someone help me.
---------------------------------------------------------------------------
Here is the VHDL code
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock5048 is port
( clock50in : in std_logic;
rst : in std_logic;
clock48out: out std_logic;
locked : out std_logic);
end clock5048;
architecture Behavioral of clock5048 is
COMPONENT dcm5048
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
begin
Inst_dcm5048: dcm5048 PORT MAP(
CLKIN_IN => clock50in,
RST_IN => rst,
CLKFX_OUT => clock48out ,
LOCKED_OUT => locked
);
end Behavioral;
--------------------------------------------------------------------------
and here is the test bench
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_5048 IS
port (clock48out: out std_logic);
END test_5048;
ARCHITECTURE behavior OF test_5048 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock5048
PORT(
clock50in : IN std_logic;
rst : IN std_logic;
clock48out : OUT std_logic;
locked : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock50in : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
-- signal clock48out : std_logic;
signal locked : std_logic;
-- Clock period definitions
constant clock50in_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock5048 PORT MAP (
clock50in => clock50in,
rst => rst,
clock48out => clock48out,
locked => locked
);
-- Clock process definitions
clock50in_process rocess
begin
clock50in <= '0';
wait for clock50in_period/2;
clock50in <= '1';
wait for clock50in_period/2;
end process;
process
begin
rst<='1'; wait for 200 ns;
rst <='0'; wait;
end process;
END;
------------------------------------------------------------------------
Simulation images have been attached