qne
Newbie level 4
hi .
i m verilog beginner . i need to know some basic questions , hope u all help me ..
=> what is difference between these two inst.
a: reg[3:0] b: wire[3:0]
what is the sequence of this code?
always @(posedge clk)
dff1 <= f(x);
assign fsm_in = f(dff1);
assign fsm_out = fsm_state;
always @(fsm_in)
fsm_state <= g(fsm_in);
i will really appericite if someone put here some examples that illustrate the concept of non blocking assignments.
regards..
i m verilog beginner . i need to know some basic questions , hope u all help me ..
=> what is difference between these two inst.
a: reg[3:0] b: wire[3:0]
what is the sequence of this code?
always @(posedge clk)
dff1 <= f(x);
assign fsm_in = f(dff1);
assign fsm_out = fsm_state;
always @(fsm_in)
fsm_state <= g(fsm_in);
i will really appericite if someone put here some examples that illustrate the concept of non blocking assignments.
regards..