need sample code for checking the msb bit of a std_logic_vector in vhdl

[ammassk]

dear all,

Please help me to write vhdl code for checking MSB bit of a std_logic_vector.

 

[willis...]

Let us assume the signal you want to check is named "test" (assuming an 8-bit std_logic_vector). Here is how you would go about checking the MSB of that signal...

signal test : std_logic_vector(7 downto 0);

begin

test_signal : process
begin
if (test(7) = '1')then
--insert code to execute when MSB = 1;
elsif (test(7) = '0') then
--insert code to execute when MSB = 0;
end if;
end process;

Regards,
Willis

 

[TrickyDicky]

or even better, for a std_logic_vector of length N (maybe its in a function, so you dont even have access to N if N was a generic):

test_signal : process
begin
if (test( test'high ) = '1')then
--insert code to execute when MSB = 1;
elsif (test( test'high ) = '0') then
--insert code to execute when MSB = 0;
end if;
end process;

 

[std_match]

This version can also handle the crazy big-endian bit numbering (0 to 7):

---

Code VHDL - [expand]
1
if test(test'left) = '1' then

---

Both little-endian and big-endian bit numbering normally have the most significant bit on the left side when a value is presented in written form.

 

[ammassk]

I used this for vhdl coding. this is not synthesisable, i think. I got error "Signal alpha cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release". I am using 10.1 version of xilinx. Can you please tell me how it make the code sythesizable?

 

[TrickyDicky]

if you posted the code, we could help you with the problem.