Need help with VHDL code

[Luciferus]

I have a Nexys2, and i need to read from an ultrasonic sensor.
This is the sensor: SRF05 Technical Documentation

Now, i'm doing my program from the Timing Diagram, it consists in two parts: enable sensor and read sensor, enable sensor part is ok because in simulation it works, but im having problems with the read part, in simulation works too, but when i try to synthetize i get this error:
Signal dist_temp cannot be synthesized, bad synchronous description.

--Variables para el sensor ultrasonico
shared variable flag: std_logic:= '0';
signal enable_temp: std_logic:= '0';
signal count_ultra: integer:= 0;
signal count_rd: integer:= 0;
signal dist_temp: std_logic_vector (7 downto 0):= "00000000";

begin

enable <= enable_temp;

[......] Counters part, it doesn't matter.

enable_sensor: process (clk_temp_1us)
begin
if (flag = '0') then
if (clk_temp_1us' event and clk_temp_1us = '1') then
count_ultra <= count_ultra + 1;
if (count_ultra >= 0 and count_ultra <= 20000) then
enable_temp <= '0';
elsif (count_ultra > 20000 and count_ultra < 20020) then
enable_temp <= '1';
elsif (count_ultra = 20020) then
count_ultra <= 0;
flag := '1';
enable_temp <= '0';
end if;
end if;
end if;
end process enable_sensor;

read_sensor: process(clk_temp_100ns, pulse_in, dist_temp)
begin
if (flag = '1') then
if (clk_temp_100ns' event and clk_temp_100ns = '1') then
if (pulse_in = '1') then
count_rd <= count_rd + 1;
if (count_rd = 144) then
count_rd <= 0;
dist_temp <= dist_temp + 1;
end if;
end if;
end if;
end if;
if (falling_edge(pulse_in)) then
flag := '0';
count_rd <= 0;
dist <= dist_temp;
dist_temp <= "00000000";
end if;
end process read_sensor;

I understand that Xilinx ISE sends that error because i'm trying to change something at both positive and negative edges of clock, i tried in different ways to write the code but i always end in the same.:sad::sad:

Any help will be appreciated

 

[vipinlal]

can you provide the timing diagram you have used to write this code.

 

[Luciferus]

 

[jducluzeau]

I understand that Xilinx ISE sends that error because i'm trying to change something at both positive and negative edges of clock, i tried in different ways to write the code but i always end in the same.:sad::sad:

In your code, dist_temp doesn't change at both rising and falling edge of clock.
dist_temp<=dist_temp+1; is synchronous to clk_temp_100ns

and


dist_temp <= "00000000"; is synchronous to pulse_in


REgards,
Jerome

 

[Luciferus]

Oh i see, in that case, what can i do? Because dist_temp must be synchronous with clk_temp_100ns (dist_temp is a counter that will be counting each 100ns) and will start counting when pulse_in is '1', but when pulse_in is '0' it must restart and give it's valor to the real "dist" which will be transfer to PC.

Is there any other way to do that?

 

[TrickyDicky]

Oh Dear. I see many problems:

1. Shared variables. basic rule is - dont use them. they are meant for simulation only. Synthesisors have a habit of making them into signals (that you should be using for inter-process communication anyway). Until you understand them, dont use them. So because you have used a shared variable, and the synthesisor is probably treating it like a signal, it will be creating logic out of clocks and your "flag" variable, when you didnt want flag to be added to logic. In reality, your logic is going to be sensitive to flag, but because it is a variable, thats not what's happening in the code.
2. 2 clocks in 1 process is usually a bad move. You're saying that "pulse_in" is a clock, which I dont think you want it to be (or if you think you do, Im saying you dont)
3. Use synchronous enables, not asynchronous ones. your life will be a lot easier.

So, as you can see, you've broken basic rules of good coding. Breaking these rules can lead to unexpected behaviour or unrealisable logic (as you have discovered). I recommend starting again, thinking about the logic first and only when you've mapped out the circuit in your head or on paper, start writing HDL code. HDL stands for "Hardware Description language". It is not a programming language (the big givaway was when you called this a "program).