need help in sample and hold design

[shineqi]

sample and hold design

I desinged a sample hold circuit for adc.

If I input 1V vpp, I cannot get 1v vpp from output.

But if I input 500mv vpp, I can get correct sampled 500mv vpp from output.

What is the reason caused this problem?

Not enough gain or not enough output swing or others?

BTW: how to simulate the trans gain to OTA and how to simulate output swing?

Thanks

 

[sanredrose]

sample and hold designs

Can you specifiy what is your Vdd ? Can you add a snapshot of the sample & hold circuit which you are designing.

Can you add little more details on what frequency your planning to operate your S&H ?

The input common mode range capability of your Sample & hold would be the reason most likely for inaccurate S&H operation. Depending upon the frequency of operation the S&H circuit architecture varies.

Added after 5 minutes:

Trans Gain ? If its an opamp then add a 100 H inductor between output and negative terminal. Add a 100 F capacitor from negative terminal to ground. Then perform an AC simulation to obtain the Open loop gain of the opamp.

To observe output swing limits, add a input signal of 500 mV Vpp and check the output while operating the Opamp in open loop mode. The point where signal swing gets clamped indicates your Output swing limits.

If your buffer is not an op amp but a source follower or emitter follower, then fixing the output common mode points plays an important role in obtaining maximum swing. You should try and fix it at Vdd/2 to ensure maximum swing.

If its not an op amp or source follower, post a snapshot of the circuit .. I can give you some help based on the snapshot ...

 

[shineqi]

snapshot mode sample and hold

I used the first stucture to do the sample and hold.

I found several problems in this citcuit.

1. Vin+ is not equal to Vin- of OTA, and there are thirty mv difference between them.

2. From the output chart, it wastes too long time to start settle and can not get a sharp pulse output. it may casue sample error.

How can I deal with them?

Thanks

Added after 9 minutes:

it is a 1.2v vdd

 

[mdcui]

in voltage buffer design, people usually cares about output voltage swing and ignores input swing, for example, a normal OP with N type diff pair biased and an current mirror device, connected like a voltage buffer, it can only work at the voltage bigger than Vtn+200mV+Idsat_mirror, use the same philosophy to check your voltage buffer.

 

[shineqi]

Would you mind explaning it more clearly?


How can I improve my input range?

Thanks

 

[mdcui]

use low vt transistor as input diff pair, and use high swing current source to supply the diff pair.