win3y
Member level 1
Hi everybody;
I need the solution for this problem:
Originally, I used 3 block RAMs (same content) with 3 separate Address reading signals.
For saving reason, I just have only one block RAM, so what the solution for this problem in case budget cycle is limited (timing constrained). If it is only two independent reading signals, the problem is easily solved by using dual-port SRAM.
Thank you very much.
W3Y
I need the solution for this problem:
Originally, I used 3 block RAMs (same content) with 3 separate Address reading signals.
For saving reason, I just have only one block RAM, so what the solution for this problem in case budget cycle is limited (timing constrained). If it is only two independent reading signals, the problem is easily solved by using dual-port SRAM.
Thank you very much.
W3Y