Nano Power Comparator

[dcv]

Dear all,

I'm searching a comparator topology suitable to work with a maximum total budget current of 100nA.

As the current budget is really low, I was wondering if it exist a topology that allows me to obtain a short delay time.

The maximum tolerable delay has to be 1us, with an over voltage of 5mV (Vin - Vref).

Actually what I have implemented is a simple cross-coupled comparator(positive feedback with hysteresis), but as I expected, I cannot achieve the spec.


Do you have any suggestions for me?


Kindest Regards

 

[erikl]

Try this (clocked) comparator architecture
... and see how fast you can get the delay with 100nA .

 

[dcv]

Thank you,

is the topology that I have already implemented but without clk, in my case is continuous time comparison. Will something change if a clock is added?

Kindest Regards

 

[erikl]

Will something change if a clock is added?

No, I don't think so, in contrary: with the reset of both Vo nodes to Vdd it will definitely take longer to get the decision as if you set the right bias to the nodes called RST.

Use min. W & L values (except for M11) in order to bring out the best speed of your process.

I think for continuous time comparison you have to add some hysteresis (some asymmetry between M3 & M4).

 

[dick_freebird]

I very much doubt a practical continuous-time CMOS comparator
operated at such low power will come anywhere close to a 5mV
Vio, let alone enough less that you consistently get usable overdrive
from a 5mV over-step. Mismatch gets worse as you starve current.
Clocked designs can at least give you an autozero to make the
most of the overdrive you are allowed. But the zero phase may
be the power hog.

 

[dcv]

I agree with you, that with this small amount of current is hard to achieve the goal.

I didn't get what you mean with "the zero phase may be the power hog."

Can you provide me a better explanation?

Thank you.

Kindest Regards