Mysterious component in VHDL

[Wild Life]

Hello ev'body, I'm tried to implement an UDP/IP stack i found in Opencore Library, everything seemed to be fine but I found an entity not supported by Xilinx ISE 12.4 (this was made by the 11 version IP core), so I have to write the code for this entity. The original code is this one:

-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity dist_mem_64x8 is
  port (
    clk : in STD_LOGIC := 'X'; 
    a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end dist_mem_64x8;

architecture STRUCTURE of dist_mem_64x8 is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal NlwRenamedSignal_qspo : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  a_2(5) <= a(5);
  a_2(4) <= a(4);
  a_2(3) <= a(3);
  a_2(2) <= a(2);
  a_2(1) <= a(1);
  a_2(0) <= a(0);
  qspo(7) <= NlwRenamedSignal_qspo(0);
  qspo(6) <= NlwRenamedSignal_qspo(0);
  qspo(5) <= NlwRenamedSignal_qspo(0);
  qspo(4) <= NlwRenamedSignal_qspo(0);
  qspo(3) <= NlwRenamedSignal_qspo(0);
  qspo(2) <= NlwRenamedSignal_qspo(0);
  qspo(1) <= NlwRenamedSignal_qspo(0);
  qspo(0) <= NlwRenamedSignal_qspo(0);
  VCC_0 : VCC
    port map (
      P => N1
    );
  GND_1 : GND
    port map (
      G => N0
    );
  BU2_XST_GND : GND
    port map (
      G => NlwRenamedSignal_qspo(0)
    );

end STRUCTURE;

So, I didn't understood at all what this component is meant to do!

There's a 6 bit input saved in a 6 bit array in an asynchronous mode.
There's an 8 bit out that only gets an one bit signal [NlwRenamedSignal_qspo] for every bit [7 downto 0] of his output
There's an obscure component named BU2_XST_GND
There are two internal signals that seems to be unused [N0 and N1]

So, I didn't understand, what is this code supposed to do? and how could I simply write the 12.4 VHDL code counterpart?

Thanks a lot!

 

[TrickyDicky]

a_2 goes nowhere, so is redundant
Im guessing the qspo is just connected to GND.

I get the feeling this used to be a graphical file that has been converted to VHDL using a code gen tool (altera does it from the file menu, I guess XST does something similar).

So, to tidy it up, just connect qspo to (others => '0).

 

[Wild Life]

But simply what does this block do? memorize a six-bit signal and output an 8 bit "00000000" only?

 

[FvM]

I don't understand, what's exactly unsupported in XST. It seems like valid VHDL at first sight. In addition, the code is marked --synthesis translate_off, so it's obviously a simulation tool that would be ignored by XST.

 

[TrickyDicky]

Nothing is memorised. Signals that are unregistered are just wires, and in this case the wires lead nowhere, so they would be trimmed if they were synthesised (and as FvM pointed out, this whole file would be ignored by XST because of the syntheses translate off pragma).

And yes, the output appears to only be all 0s

 

[Wild Life]

So this is useless at all! Am I wrong?

---------- Post added at 11:41 ---------- Previous post was at 11:38 ----------

This was supposed to be a LUT memory, or something similar

 

[permute]

this looks like someone had originally written HDL for a module, then later synthesized and implemented it, then regenerated the HDL from the implementation.

It's pretty clear that this was, at one point intended to be a 64x8 RAM of some sort. if you look at the SLICEM you'll see references to things like qspo IIRC.

 

[Wild Life]

I solved, it seemed to be a registered rom made with IP CORE

 

[TrickyDicky]

This code is not a registered ROM.

 

[FvM]

As said, it's a simulation file. If you review the UDP core, everything is clear at once. There's a pair of coregen and simulation files for this and a few more components. The spartan version of the simulation file however seems to be broken, there's also a virtex version, that contains a reasonable ROM simulation.

If at least the full file had been shown with the initial post, including the header, most speculations could be avoided. My suggestion is to get an overview of the design structure first before asking questions about individual files or even snippets.

 

[lucbra]

It's indeed a ROM generated by Xilinx' toolchain - like said above probably a lookup table of 64 bytes (maybe the header of the UDP telegram?)