Multiply two signals in VHDL with FPGA output

[uselessmail]

Hi there!
I wrote two programs in VHDL, one to generate a PRBS sequence and another to generate a square signal of 100 Mhz. For both these signals I took the output at the SMA port on the FPGA board (Xilinx SP601). Now I want to multiply these two signals and get the output again at the SMA port.

For the PRBS sequence, I got the output in the register

data_out std_logic_vector (9 downto 0)

. To get the data serially out from the SMA port I created another register 'mlbs_out' which is an 'std_logic'. I copied the data into mlbs_out in the following manner:

mlbs_out <= data_out(9);
data_out(9 downto 1) <= data_out(8 downto 0);

For the square signal, I simply got the output in a register 'bout' which is an 'std_logic'

Now when I use the simple multiplication operator I get an error. The code I use is:

LED_OUT <= ((mlbs_out)*(bout));

The error I get is, "found '0' definitions of operator "*", cannot determine exact overloaded matching definition for "*" "
I am using "STD_LOGIC_UNSIGNED.ALL" library. I also tried using the "ARITHMETIC.ALL" library and then writing the sign of the signals everywhere but to no avail.
Could someone please explain how I can get over this problem?

 

[TrickyDicky]

First of all, you have to understand that a std_logic, on its own, is not a number. Its just a single bit. Also understand that a std_logic_vector, is also not a number, it is a collection of bits. So before you are doing any arithmatic, you need to convert to a type that does represent a number.

This is possible using the numeric_std library. The std_logic_unsigned/signed and arith libraries are non-standard VHDL, and should not be used.

but the question is, why would you multiply two 1-bit numbers, why not just AND them together?

 

[ravics]

You could use Multiplier IP Core as you're using Xilinx SP601.