[MOVED]Layout Considerations to reduce 1/f noise

[ckaven]

Hello,
I am relatively new to PCB layout. I was wondering if anyone on here has any considerations or do's and donts to reduce 1/f noise in an analog circuit. I cant change the ICs being used due to power and customer restraints, so the noise generated by them is what it is. I was wondering if certain routing techniques, trace length, trace width, copper weight, etc. could be changed to improve the noise floor below 10Hz. I have tried all the ICs available in my power range and have had little improvement. I wanted to get some advice on layout before attempting a redo. Any help would be much appreciated.

thanks

 

[biff44]

what is the applicatoin/frequency range?

 

[ckaven]

application is low frequency analog. range of interest .01-1000Hz. problem is a rise in noise floor below 10Hz

 

[biff44]

My knowledge of 1/f noise is more in the RF range, but I will take a ***** at it. Layout can reduce noise pickup at these low frequencies. Proper shielding can help a lot. Also if the input impdeances are high, a guard ring around the inputs helps, as does removing the solder mask from the board in the input area.

If you are stuck with a certain semiconductor that has high 1/f noise, then some sort of feedback might help. If it is just a transistor, some emitter to ground resistance should reduce the 1/f noise. If you can add a negative feedback op amp in parallel with the device you are stuck with, that should help to degenerate the 1/f noise.

 

[dave9000]

hi ckaven,
I find that below 0.1Hz it gets difficult to tell if the measured noise is 1/f from some component or just thermal noise - by thermal noise I mean the effect of the environment temperature on the circuit.
Depending on the sensitivity of your circuit this may be the dominant contribution.
I found interesting tips in this respect in the datasheet of the LTZ1000 voltage reference: minimize thermal gradients by using tracks of the same size/length and shield as much as you can.
It looks like black magic when you read it, but really a flow of air on the circuit generates noise!
Also, depending on your application, you may consider implementing the usual design techniques: correlated double sampling, lock-in, etc...

 

[ckaven]

Thanks biff and dave. I have notice the effects of thermal noise on the board. All feedback resistors in the design are 1M. If i change them to 10k the noise in the low region improves by a couple dB, but it also increases the power draw to an unacceptable level.
biff44- I havent seen guard rings around op amp inputs before. Does this accomplish the same noise reduction as removing ground and power planes from underneath +IN and -IN terminals. I read an App Note claiming that solid planes underneath op amp terminals caused a capacitive coupling that can introduce noise. I usually 'flood' the analog portion of my circuit boards with a ground pour, but this design is too dense for that. All the ICs in the design are very high imp. input. Mainly op amps and 1 INA. I dont have the ability to add any more feedback due to the tight power constraints.

 

[ckaven]

A coworker suggested that i change my bypass and bulk capacitors. He claims that he has seen cases were using ceramics with too low of esr can increase 1/f noise. Have either of you ever heard of that happening?

 

[keith1200rs]

I have found that very low frequency noise can be improved by using larger decoupling capacitors. In one specific case I had 10nF & 10uF on every IC. Increasing the 10uF to 100uF reduced the LF noise (these were boards working down to 0.02Hz as I recall).

Keith.

 

[dave9000]

Some voltage regulators, expecially LDOs, may become noisy - or even unstable - if the ESR is too low.
But I wonder if this excess noise is really 1/f.
If you suspect that the noise you are seeing is from the power supply you should perform a spectral analysis of the supply lines.

P.S. in my experience increasing the decoupling capacitors does not improve things.

 

[FvM]

In my opinion, the first point would be sorting out the different sources of 1/f noise. Thermal fluctuations play a huge role particularly with single ended transistor stages, and in special cases with thermolectric generated voltages. They can be mostly cut by good thermal shielding of the circuit board, including filling the internal enclosure voids with e.g. cotton wool, at least for test.

The expectable basic electronic noise (there may be unexpected source of excessive noise of course) should be determined in a SPICE noise analysis. In my view, most cases of "excessive" noise, that have been recently discussed at Edaboard can be related to unawareness of dominant noise sources, e.g. voltage references.

PCB layout probably isn't the most important factor. A good electrical and thermal ground should be provided however.

 

[ckaven]

I dont believe that thermal noise is the dominate issue. The pcb is sitting on a bare hard surface in a room that averages about 20C. There is also very little heat produced during operation due to the fact that the entire circuit only draws a max of 200uA. I plan to do spectral analysis of power rails first thing next week. The design as 2 LDOs and a switched cap inverter. I believe all grounding is pretty solid. Its a 4 layer pcb with stack up sig-gnd-power-signal. The switching frequency of inverter is ~10kHz and is filter by multiple stages of ferrite beads and large caps. The previous version of this design was on a pcb twice the size with parts that were more high power and better noise characteristics. Everything was spaced out very nicely and a ground pour present around all signal components. Once i have tested power rails i plan to replace all components with previously used ones and see how much noise is related to current parts and how much to physical layout. Thank you all for your comments and suggestions. I will post results as i get them.