[Moved]: How to increase fan-out count of a net without changing functionality?

[Sumathigokul]

Hi...

Have a Nice day..

For a FPGA (PROASIC3, Libero IDE v9.1) based digital design, I want to increase fan-out count of a net without changing the original functionality. So i instantiated a combination of AND and XOR gates with enable input with*that particular net (say net1) as mentioned below.

Gate1: AND2 port map (A=> net1, B=> enable, Y => net2);

Gate2: XOR2 port map (A=> net1, B=>net2, c=>net_next_circuit);

So, whenever enable=0, net1 value is resumed. i instantiated the same logic thrice to make fan-out count of net1 as 4 (along with already existing instantiation) but these modules are optimized in synthesis. How to resume these modules in the design?

I used syn_keep or*syn_preserve attributes, even then tool does optimization.*

Please give me any solution.

Thank you in advance.

 

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First of all why are you doing this? If you are having problems with timing adding gates in the path won't fix that. The ProASIC3 is a slow FPGA it's not a real ASIC where you can upsize a buffer.

Next question is what tool optimizes? Synplify should accept the syn_keep on nets and the syn_preserve on FFs and the output net. Is the removal of the logic in Libero? I quickly searched the Libero user guide but didn't find anything related to disabling redundant logic removal.